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-rw-r--r--src/mainboard/ibm/Kconfig16
-rw-r--r--src/mainboard/ibm/Kconfig.name2
-rw-r--r--src/mainboard/ibm/e325/Kconfig58
-rw-r--r--src/mainboard/ibm/e325/Kconfig.name2
-rw-r--r--src/mainboard/ibm/e325/board_info.txt2
-rw-r--r--src/mainboard/ibm/e325/cmos.layout60
-rw-r--r--src/mainboard/ibm/e325/devicetree.cb69
-rw-r--r--src/mainboard/ibm/e325/irq_tables.c60
-rw-r--r--src/mainboard/ibm/e325/mptable.c133
-rw-r--r--src/mainboard/ibm/e325/resourcemap.c271
-rw-r--r--src/mainboard/ibm/e325/romstage.c119
-rw-r--r--src/mainboard/ibm/e326/Kconfig58
-rw-r--r--src/mainboard/ibm/e326/Kconfig.name2
-rw-r--r--src/mainboard/ibm/e326/board_info.txt2
-rw-r--r--src/mainboard/ibm/e326/cmos.layout60
-rw-r--r--src/mainboard/ibm/e326/devicetree.cb73
-rw-r--r--src/mainboard/ibm/e326/irq_tables.c60
-rw-r--r--src/mainboard/ibm/e326/mptable.c132
-rw-r--r--src/mainboard/ibm/e326/resourcemap.c271
-rw-r--r--src/mainboard/ibm/e326/romstage.c119
20 files changed, 0 insertions, 1569 deletions
diff --git a/src/mainboard/ibm/Kconfig b/src/mainboard/ibm/Kconfig
deleted file mode 100644
index 256fefe52d..0000000000
--- a/src/mainboard/ibm/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_IBM
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/ibm/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/ibm/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "IBM"
-
-endif # VENDOR_IBM
diff --git a/src/mainboard/ibm/Kconfig.name b/src/mainboard/ibm/Kconfig.name
deleted file mode 100644
index 7f3cb17a62..0000000000
--- a/src/mainboard/ibm/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_IBM
- bool "IBM"
diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig
deleted file mode 100644
index 04006771d8..0000000000
--- a/src/mainboard/ibm/e325/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-if BOARD_IBM_E325
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_AMD8111
- select SOUTHBRIDGE_AMD_AMD8131
- select SUPERIO_NSC_PC87366
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
-
-config MAINBOARD_DIR
- string
- default ibm/e325
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x1000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "eServer 325"
-
-config MAX_CPUS
- int
- default 1
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x1
-
-config IRQ_SLOT_COUNT
- int
- default 12
-
-endif # BOARD_IBM_E325
diff --git a/src/mainboard/ibm/e325/Kconfig.name b/src/mainboard/ibm/e325/Kconfig.name
deleted file mode 100644
index 7a0ea83a66..0000000000
--- a/src/mainboard/ibm/e325/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_IBM_E325
- bool "eServer 325"
diff --git a/src/mainboard/ibm/e325/board_info.txt b/src/mainboard/ibm/e325/board_info.txt
deleted file mode 100644
index 5bb0bcaea5..0000000000
--- a/src/mainboard/ibm/e325/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-53255
diff --git a/src/mainboard/ibm/e325/cmos.layout b/src/mainboard/ibm/e325/cmos.layout
deleted file mode 100644
index 4e081ea1aa..0000000000
--- a/src/mainboard/ibm/e325/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb
deleted file mode 100644
index f63249d02a..0000000000
--- a/src/mainboard/ibm/e325/devicetree.cb
+++ /dev/null
@@ -1,69 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_940
- device lapic 0 on end
- end
- end
- device domain 0 on
- chip northbridge/amd/amdk8
- device pci 18.0 on end # LDT 0
- device pci 18.0 on # LDT 1
- chip southbridge/amd/amd8131
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 on end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/nsc/pc87366
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 off # Com 2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Com 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.4 off end # SWC
- device pnp 2e.5 off end # Mouse
- device pnp 2e.6 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.7 off end # GPIO
- device pnp 2e.8 off end # ACB
- device pnp 2e.9 off end # FSCM
- device pnp 2e.a off end # WDT
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 off end
- device pci 1.6 off end
- end
- end # device pci 18.0
- device pci 18.0 on end # LDT2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/ibm/e325/irq_tables.c b/src/mainboard/ibm/e325/irq_tables.c
deleted file mode 100644
index 24987b7e00..0000000000
--- a/src/mainboard/ibm/e325/irq_tables.c
+++ /dev/null
@@ -1,60 +0,0 @@
-#include <arch/pirq_routing.h>
-#include <device/pci.h>
-
-#define IRQ_ROUTER_BUS 0
-#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
-#define IRQ_ROUTER_VENDOR 0x1022
-#define IRQ_ROUTER_DEVICE 0x746b
-
-#define AVAILABLE_IRQS 0xdef8
-#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
- { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
- {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
-
-/* Each IRQ_SLOT entry consists of:
- * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
- */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
- IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
- IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- IRQ_ROUTER_VENDOR, /* Vendor */
- IRQ_ROUTER_DEVICE, /* Device */
- 0x00, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x34, /* u8 checksum , mod 256 checksum must give zero */
- { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
- /* Northbridge, Node 0 */
- IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0),
- /* AMD-8131 PCI-X Bridge */
- IRQ_SLOT(0x0, 0x01,0x01,0x0, 0,0,0,0),
- /* Onboard LSI SCSI Controller */
- IRQ_SLOT(0x0, 0x02,0x02,0x0, 3,0,0,0),
- /* Onboard Broadcom NICs */
- IRQ_SLOT(0x0, 0x02,0x01,0x0, 1,2,0,0),
- /* AMD-8131 PCI-X Bridge */
- IRQ_SLOT(0x0, 0x01,0x02,0x0, 0,0,0,0),
- /* PCI Slot 1-2 */
- IRQ_SLOT(0x1, 0x03,0x03,0x0, 1,2,3,4),
- IRQ_SLOT(0x2, 0x03,0x04,0x0, 2,3,4,1),
- /* AMD-8111 PCI Bridge */
- IRQ_SLOT(0x0, 0x01,0x03,0x0, 0,0,0,0),
- /* USB Controller */
- IRQ_SLOT(0x0, 0x04,0x00,0x0, 0,0,0,4),
- /* ATI Rage XL VGA */
- IRQ_SLOT(0x0, 0x04,0x05,0x0, 1,0,0,0),
- /* AMD-8111 LPC Dridge */
- IRQ_SLOT(0x0, 0x01,0x04,0x0, 0,0,0,0),
- /* Northbridge, Node 1 */
- IRQ_SLOT(0x0, 0x00,0x19,0x0, 0,0,0,0),
-
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
deleted file mode 100644
index 1dad72c6e1..0000000000
--- a/src/mainboard/ibm/e325/mptable.c
+++ /dev/null
@@ -1,133 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
-
- int bus_isa;
- unsigned char bus_8111_0;
- unsigned char bus_8111_1;
- unsigned char bus_8131_1;
- unsigned char bus_8131_2;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- {
- device_t dev;
-
- /* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
- if (dev) {
- bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
- bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
- bus_8111_0 = 1;
- bus_8111_1 = 4;
- }
-
- /* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
- bus_8131_1 = 2;
- }
-
- /* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
- bus_8131_2 = 3;
- }
- }
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
- {
- device_t dev;
- struct resource *res;
- /* 8131-1 apic #3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x03, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- /* 8131-2 apic #4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x04, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
-
- /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
- /* Integrated SMBus 2.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
- /* Integrated AMD AC97 Audio */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
-
- /* Integrated AMD USB */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
-
- /* On board ATI Rage XL */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
-
- /* On board Broadcom nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
-
- /* On board LSI SCSI */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
-
- /* PCI Slot 1 PCIX */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
-
- /* PCI Slot 2 PCIX */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
-
- /* Standard local interrupt assignments:
- * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c
deleted file mode 100644
index 85aafbf5a7..0000000000
--- a/src/mainboard/ibm/e325/resourcemap.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * IBM E325 needs a different resource map
- *
- */
-
-static void setup_ibm_e325_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
-
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
- //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
- // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
- PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
- //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
- //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
- PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
- //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
- //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
- PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
- //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
- //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
- PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
- PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
- PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
- PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
- PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
- };
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
deleted file mode 100644
index 48e7de83b1..0000000000
--- a/src/mainboard/ibm/e325/romstage.c
+++ /dev/null
@@ -1,119 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <stdlib.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <superio/nsc/pc87366/pc87366.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include "southbridge/amd/amd8111/early_ctrl.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
- } else {
- /* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset high. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
- udelay(90);
- }
-}
-
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "resourcemap.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const struct mem_controller cpu[] = {
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { DIMM0, DIMM2, 0, 0 },
- .channel1 = { DIMM1, DIMM3, 0, 0 },
- },
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { DIMM4, DIMM6, 0, 0 },
- .channel1 = { DIMM5, DIMM7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
-
- if (bist == 0)
- init_cpus(cpu_init_detectedx);
-
- pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_ibm_e325_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
-#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
-#endif
- // automatically set that for you, but you might meet tight space
- needs_reset |= ht_setup_chains_x();
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- enable_smbus();
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
- post_cache_as_ram();
-}
diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig
deleted file mode 100644
index bd2bb26c6f..0000000000
--- a/src/mainboard/ibm/e326/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-if BOARD_IBM_E326
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_AMD8111
- select SOUTHBRIDGE_AMD_AMD8131
- select SUPERIO_NSC_PC87366
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select BOARD_ROMSIZE_KB_512
- select QRANK_DIMM_SUPPORT
-
-config MAINBOARD_DIR
- string
- default ibm/e326
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x1000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "eServer 326"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x1
-
-config IRQ_SLOT_COUNT
- int
- default 12
-
-endif # BOARD_IBM_E326
diff --git a/src/mainboard/ibm/e326/Kconfig.name b/src/mainboard/ibm/e326/Kconfig.name
deleted file mode 100644
index 138fd5174d..0000000000
--- a/src/mainboard/ibm/e326/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_IBM_E326
- bool "eServer 326"
diff --git a/src/mainboard/ibm/e326/board_info.txt b/src/mainboard/ibm/e326/board_info.txt
deleted file mode 100644
index af5631ef6b..0000000000
--- a/src/mainboard/ibm/e326/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-58655
diff --git a/src/mainboard/ibm/e326/cmos.layout b/src/mainboard/ibm/e326/cmos.layout
deleted file mode 100644
index 4e081ea1aa..0000000000
--- a/src/mainboard/ibm/e326/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb
deleted file mode 100644
index 32d04a7fa9..0000000000
--- a/src/mainboard/ibm/e326/devicetree.cb
+++ /dev/null
@@ -1,73 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_940
- device lapic 0 on end
- end
- end
-
- device domain 0 on
- chip northbridge/amd/amdk8
- device pci 18.0 on end # LDT 0
- device pci 18.0 on # LDT 1
- chip southbridge/amd/amd8131
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 on end
- device pci 1.0 off end
- device pci 5.0 on end # ATI Rage XL
- end
- device pci 1.0 on
- chip superio/nsc/pc87366
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 off # Com 2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Com 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.4 off end # SWC
- device pnp 2e.5 off end # Mouse
- device pnp 2e.6 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.7 off end # GPIO
- device pnp 2e.8 off end # ACB
- device pnp 2e.9 off end # FSCM
- device pnp 2e.a off end # WDT
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 off end
- device pci 1.6 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- end
- end # device pci 18.0
- device pci 18.0 on end # LDT2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c
deleted file mode 100644
index 24987b7e00..0000000000
--- a/src/mainboard/ibm/e326/irq_tables.c
+++ /dev/null
@@ -1,60 +0,0 @@
-#include <arch/pirq_routing.h>
-#include <device/pci.h>
-
-#define IRQ_ROUTER_BUS 0
-#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
-#define IRQ_ROUTER_VENDOR 0x1022
-#define IRQ_ROUTER_DEVICE 0x746b
-
-#define AVAILABLE_IRQS 0xdef8
-#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
- { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
- {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
-
-/* Each IRQ_SLOT entry consists of:
- * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
- */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
- IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
- IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- IRQ_ROUTER_VENDOR, /* Vendor */
- IRQ_ROUTER_DEVICE, /* Device */
- 0x00, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x34, /* u8 checksum , mod 256 checksum must give zero */
- { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
- /* Northbridge, Node 0 */
- IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0),
- /* AMD-8131 PCI-X Bridge */
- IRQ_SLOT(0x0, 0x01,0x01,0x0, 0,0,0,0),
- /* Onboard LSI SCSI Controller */
- IRQ_SLOT(0x0, 0x02,0x02,0x0, 3,0,0,0),
- /* Onboard Broadcom NICs */
- IRQ_SLOT(0x0, 0x02,0x01,0x0, 1,2,0,0),
- /* AMD-8131 PCI-X Bridge */
- IRQ_SLOT(0x0, 0x01,0x02,0x0, 0,0,0,0),
- /* PCI Slot 1-2 */
- IRQ_SLOT(0x1, 0x03,0x03,0x0, 1,2,3,4),
- IRQ_SLOT(0x2, 0x03,0x04,0x0, 2,3,4,1),
- /* AMD-8111 PCI Bridge */
- IRQ_SLOT(0x0, 0x01,0x03,0x0, 0,0,0,0),
- /* USB Controller */
- IRQ_SLOT(0x0, 0x04,0x00,0x0, 0,0,0,4),
- /* ATI Rage XL VGA */
- IRQ_SLOT(0x0, 0x04,0x05,0x0, 1,0,0,0),
- /* AMD-8111 LPC Dridge */
- IRQ_SLOT(0x0, 0x01,0x04,0x0, 0,0,0,0),
- /* Northbridge, Node 1 */
- IRQ_SLOT(0x0, 0x00,0x19,0x0, 0,0,0,0),
-
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
deleted file mode 100644
index 46dabd3893..0000000000
--- a/src/mainboard/ibm/e326/mptable.c
+++ /dev/null
@@ -1,132 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
-
- int bus_isa;
- unsigned char bus_8111_0;
- unsigned char bus_8111_1;
- unsigned char bus_8131_1;
- unsigned char bus_8131_2;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- {
- device_t dev;
-
- /* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
- if (dev) {
- bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
- bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
- bus_8111_0 = 1;
- bus_8111_1 = 4;
- }
-
- /* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
- bus_8131_1 = 2;
- }
-
- /* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
- bus_8131_2 = 3;
- }
- }
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
- {
- device_t dev;
- struct resource *res;
- /* 8131-1 apic #3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x03, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- /* 8131-2 apic #4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x04, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
-
- /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
- /* Integrated SMBus 2.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
- /* Integrated AMD AC97 Audio */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
-
- /* Integrated AMD USB */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
-
- /* On board ATI Rage XL */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
-
- /* On board Broadcom nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
-
- /* On board LSI SCSI */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
-
- /* PCI Slot 1 PCIX */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
-
- /* PCI Slot 2 PCIX */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
-
- /* Standard local interrupt assignments:
- * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/ibm/e326/resourcemap.c b/src/mainboard/ibm/e326/resourcemap.c
deleted file mode 100644
index 98fdcc0ec6..0000000000
--- a/src/mainboard/ibm/e326/resourcemap.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * IBM E325 needs a different resource map
- *
- */
-
-static void setup_ibm_e326_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
-
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
- //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
- // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
- PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
- //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
- //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
- PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
- //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
- //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
- PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
- //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
- //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
-
- PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
- PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
- PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
- PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
- PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
- PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
- };
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
deleted file mode 100644
index a27a2189b5..0000000000
--- a/src/mainboard/ibm/e326/romstage.c
+++ /dev/null
@@ -1,119 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <stdlib.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <superio/nsc/pc87366/pc87366.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/early_ctrl.c"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
- } else {
- /* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset high. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
- udelay(90);
- }
-}
-
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "resourcemap.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const struct mem_controller cpu[] = {
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { DIMM0, DIMM2, 0, 0 },
- .channel1 = { DIMM1, DIMM3, 0, 0 },
- },
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { DIMM4, DIMM6, 0, 0 },
- .channel1 = { DIMM5, DIMM7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
-
- if (bist == 0)
- init_cpus(cpu_init_detectedx);
-
- pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_ibm_e326_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
-#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
-#endif
- // automatically set that for you, but you might meet tight space
- needs_reset |= ht_setup_chains_x();
-
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- enable_smbus();
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
- post_cache_as_ram();
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 09:00:24 +0000