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-rw-r--r--src/southbridge/intel/fsp_rangeley/Kconfig1
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.h9
2 files changed, 3 insertions, 7 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index 919d963c54..092cf1dd63 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -21,6 +21,7 @@ if SOUTHBRIDGE_INTEL_FSP_RANGELEY
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index ba0fa4e8c5..0674dcae4f 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -18,6 +18,8 @@
#ifndef SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
#define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
+#include <arch/acpi.h>
+
/* SOC types */
#define SOC_TYPE_RANGELEY 0x1F
@@ -316,13 +318,6 @@ void rangeley_sb_early_initialization(void);
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)