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-rw-r--r--src/soc/amd/stoneyridge/bootblock/bootblock.c9
-rw-r--r--src/soc/amd/stoneyridge/chip.h9
-rw-r--r--src/soc/amd/stoneyridge/gpio.c102
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h29
4 files changed, 149 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index c2440b0eb1..479e0fc9f2 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -93,6 +93,15 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
void bootblock_soc_early_init(void)
{
+ /*
+ * This call (sb_reset_i2c_slaves) was originally early at
+ * bootblock_c_entry, but had to be moved here. There was an
+ * unexplained delay in the middle of the i2c transaction when
+ * we had it in bootblock_c_entry. Moving it to this point
+ * (or adding delays) fixes the issue. It seems like the processor
+ * just pauses but we don't know why.
+ */
+ sb_reset_i2c_slaves();
bootblock_fch_early_init();
post_code(0x90);
}
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 4cf2b33596..8ed8e4d903 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -50,6 +50,15 @@ struct soc_amd_stoneyridge_config {
/* Used if UMAMODE_SPECIFIED_SIZE is set. */
size_t uma_size;
+ /*
+ * If sb_reset_i2c_slaves() is called, this devicetree register
+ * defines which I2C SCL will be toggled 9 times at 100 KHz.
+ * For example, should we need I2C0 and I2C3 have their slave
+ * devices reseted by toggling SCL, use:
+ *
+ * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
+ */
+ u8 i2c_scl_reset;
struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
u8 stapm_percent;
u32 stapm_time;
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index b469f820b2..cc54f2c82d 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -17,8 +17,10 @@
#include <arch/io.h>
#include <console/console.h>
+#include <delay.h>
#include <gpio.h>
#include <soc/gpio.h>
+#include <soc/pci_devs.h>
#include <soc/southbridge.h>
#include <assert.h>
@@ -237,6 +239,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
write8(mux_ptr, mux & AMD_GPIO_MUX_MASK);
+ read8(mux_ptr); /* Flush posted write */
/* special case if pin 2 is assigned to wake */
if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK))
route_sci(GPIO_2_EVENT);
@@ -296,6 +299,105 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
edge_level, mask);
}
+/*
+ * I2C pins are open drain with external pull up, so in order to bit bang them
+ * all, SCL pins must become GPIO inputs with no pull, then they need to be
+ * toggled between input-no-pull and output-low. This table is for the initial
+ * conversion of all SCL pins to input with no pull.
+ */
+static const struct soc_amd_gpio i2c_2_gpi[] = {
+ PAD_GPI(I2C0_SCL_PIN, PULL_NONE),
+ PAD_GPI(I2C1_SCL_PIN, PULL_NONE),
+ PAD_GPI(I2C2_SCL_PIN, PULL_NONE),
+ PAD_GPI(I2C3_SCL_PIN, PULL_NONE),
+};
+#define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
+
+/*
+ * To program I2C pins without destroying their programming, the registers
+ * that will be changed need to be saved first.
+ */
+static void save_i2c_pin_registers(uint8_t gpio,
+ struct soc_amd_i2c_save *save_table)
+{
+ uint32_t *gpio_ptr;
+ uint8_t *mux_ptr;
+
+ mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+ gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+ save_table->mux_value = read8(mux_ptr);
+ save_table->control_value = read32(gpio_ptr);
+}
+
+static void restore_i2c_pin_registers(uint8_t gpio,
+ struct soc_amd_i2c_save *save_table)
+{
+ uint32_t *gpio_ptr;
+ uint8_t *mux_ptr;
+
+ mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+ gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+ write8(mux_ptr, save_table->mux_value);
+ read8(mux_ptr);
+ write32(gpio_ptr, save_table->control_value);
+ read32(gpio_ptr);
+}
+
+/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
+void sb_reset_i2c_slaves(void)
+{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+ struct soc_amd_i2c_save save_table[saved_pins_count];
+ uint8_t i, j, control;
+
+ if (!dev || !dev->chip_info)
+ return;
+ cfg = dev->chip_info;
+ control = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ if (control == 0)
+ return;
+
+ /* Save and reprogram I2C SCL pins */
+ for (i = 0; i < saved_pins_count; i++)
+ save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
+ sb_program_gpios(i2c_2_gpi, saved_pins_count);
+
+ /*
+ * Toggle SCL back and forth 9 times under 100KHz. A single read is
+ * needed after the writes to force the posted write to complete.
+ */
+ for (j = 0; j < 9; j++) {
+ if (control & GPIO_I2C0_SCL)
+ write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW);
+ if (control & GPIO_I2C1_SCL)
+ write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW);
+ if (control & GPIO_I2C2_SCL)
+ write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW);
+ if (control & GPIO_I2C3_SCL)
+ write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW);
+
+ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
+
+ if (control & GPIO_I2C0_SCL)
+ write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH);
+ if (control & GPIO_I2C1_SCL)
+ write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH);
+ if (control & GPIO_I2C2_SCL)
+ write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH);
+ if (control & GPIO_I2C3_SCL)
+ write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH);
+
+ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+ udelay(4);
+ }
+
+ /* Restore I2C pins. */
+ for (i = 0; i < saved_pins_count; i++)
+ restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
+}
+
int gpio_interrupt_status(gpio_t gpio)
{
uintptr_t gpio_address = gpio_get_address(gpio);
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 6e722933b8..b758309c75 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -36,6 +36,17 @@ struct soc_amd_event {
uint8_t event;
};
+struct soc_amd_i2c_save {
+ uint32_t control_value;
+ uint8_t mux_value;
+};
+
+#define GPIO_I2C0_SCL BIT(0)
+#define GPIO_I2C1_SCL BIT(1)
+#define GPIO_I2C2_SCL BIT(2)
+#define GPIO_I2C3_SCL BIT(3)
+#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
#define GPIO_TOTAL_PINS 149
#define GPIO_PIN_IN (1 << 0) /* for byte access */
#define GPIO_PIN_OUT (1 << 6) /* for byte access */
@@ -171,6 +182,18 @@ struct soc_amd_event {
#define GPIO_147 147
#define GPIO_148 148
+#define I2C0_SCL_PIN GPIO_145
+#define I2C1_SCL_PIN GPIO_147
+#define I2C2_SCL_PIN GPIO_113
+#define I2C3_SCL_PIN GPIO_19
+
+#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN)
+#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN)
+#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
+#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
+#define GPIO_SCL_HIGH 0
+#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE
+
/* IOMUX function names and values generated from BKDG. */
#define GPIO_0_IOMUX_PWR_BTN_L 0
#define GPIO_0_IOMUX_GPIOxx 1
@@ -346,6 +369,11 @@ struct soc_amd_event {
#define GPIO_148_IOMUX_I2C1_SDA 0
#define GPIO_148_IOMUX_GPIOxx 1
+#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx
+#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx
+#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx
+#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
+
enum {
GEVENT_0,
GEVENT_1,
@@ -571,6 +599,7 @@ uintptr_t gpio_get_address(gpio_t gpio_num);
* @return none
*/
void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size);
+void sb_reset_i2c_slaves(void);
/* Return the interrupt status and clear if set. */
int gpio_interrupt_status(gpio_t gpio);
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 05:07:30 +0000