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-rw-r--r--src/mainboard/sifive/hifive-unleashed/romstage.c2
-rw-r--r--src/soc/sifive/fu540/include/soc/addressmap.h1
-rw-r--r--src/soc/sifive/fu540/sdram.c38
-rw-r--r--src/soc/sifive/fu540/ux00ddr.h202
4 files changed, 242 insertions, 1 deletions
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index 9729f86f4a..df4cf894b2 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -40,5 +40,7 @@ void main(void)
uart_init(CONFIG_UART_FOR_CONSOLE);
#endif
+ sdram_init();
+
run_ramstage();
}
diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h
index 0de1423ae2..21709b5443 100644
--- a/src/soc/sifive/fu540/include/soc/addressmap.h
+++ b/src/soc/sifive/fu540/include/soc/addressmap.h
@@ -29,6 +29,7 @@
#define FU540_ETHMAC 0x10090000
#define FU540_ETHMGMT 0x100a0000
#define FU540_DDRCTRL 0x100b0000
+#define FU540_DDRBUSBLOCKER 0x100b8000
#define FU540_DDRMGMT 0x100c0000
#define FU540_QSPI0FLASH 0x20000000
#define FU540_QSPI1FLASH 0x30000000
diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c
index 1ad36da2b3..6418b0d6e3 100644
--- a/src/soc/sifive/fu540/sdram.c
+++ b/src/soc/sifive/fu540/sdram.c
@@ -14,10 +14,46 @@
*/
#include <soc/sdram.h>
+#include <soc/addressmap.h>
+
+#include "regconfig-phy.h"
+#include "regconfig-ctl.h"
+#include "ux00ddr.h"
+
+#define DENALI_PHY_DATA ddr_phy_settings
+#define DENALI_CTL_DATA ddr_ctl_settings
+#include "ddrregs.h"
+
+#define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL)
+#define DDRCTLPLL_F 55
+#define DDRCTLPLL_Q 2
void sdram_init(void)
{
- // TODO: implement
+ ux00ddr_writeregmap(FU540_DDRCTRL, ddr_ctl_settings, ddr_phy_settings);
+ ux00ddr_disableaxireadinterleave(FU540_DDRCTRL);
+
+ ux00ddr_disableoptimalrmodw(FU540_DDRCTRL);
+
+ ux00ddr_enablewriteleveling(FU540_DDRCTRL);
+ ux00ddr_enablereadleveling(FU540_DDRCTRL);
+ ux00ddr_enablereadlevelinggate(FU540_DDRCTRL);
+ if (ux00ddr_getdramclass(FU540_DDRCTRL) == DRAM_CLASS_DDR4)
+ ux00ddr_enablevreftraining(FU540_DDRCTRL);
+
+ //mask off interrupts for leveling completion
+ ux00ddr_mask_leveling_completed_interrupt(FU540_DDRCTRL);
+
+ ux00ddr_mask_mc_init_complete_interrupt(FU540_DDRCTRL);
+ ux00ddr_mask_outofrange_interrupts(FU540_DDRCTRL);
+ ux00ddr_setuprangeprotection(FU540_DDRCTRL, DDR_SIZE);
+ ux00ddr_mask_port_command_error_interrupt(FU540_DDRCTRL);
+
+ const uint64_t ddr_size = DDR_SIZE;
+ const uint64_t ddr_end = FU540_DRAM + ddr_size;
+ ux00ddr_start(FU540_DDRCTRL, FU540_DDRBUSBLOCKER, ddr_end);
+
+ ux00ddr_phy_fixup(FU540_DDRCTRL);
}
size_t sdram_size_mb(void)
diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h
new file mode 100644
index 0000000000..fc5e110421
--- /dev/null
+++ b/src/soc/sifive/fu540/ux00ddr.h
@@ -0,0 +1,202 @@
+/* Copyright (c) 2018 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* See the file LICENSE for further information */
+
+#ifndef _SIFIVE_UX00DDR_H
+#define _SIFIVE_UX00DDR_H
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
+
+#define DRAM_CLASS_OFFSET 8
+#define DRAM_CLASS_DDR4 0xA
+#define OPTIMAL_RMODW_EN_OFFSET 0
+#define DISABLE_RD_INTERLEAVE_OFFSET 16
+#define OUT_OF_RANGE_OFFSET 1
+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
+#define MC_INIT_COMPLETE_OFFSET 8
+#define LEVELING_OPERATION_COMPLETED_OFFSET 22
+#define DFI_PHY_WRLELV_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET 16
+#define RDLVL_GATE_EN_OFFSET 24
+#define WRLVL_EN_OFFSET 0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET 0
+#define PHY_RX_CAL_DQ1_0_OFFSET 16
+
+static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) {
+ unsigned int i;
+ for (i=1152;i<=1214;i++) {
+ uint32_t physet = physettings[i];
+ /*if (physet!=0)*/ ddrphyreg[i] = physet;
+ }
+ for (i=0;i<=1151;i++) {
+ uint32_t physet = physettings[i];
+ /*if (physet!=0)*/ ddrphyreg[i] = physet;
+ }
+}
+
+
+static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) {
+ volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr;
+ volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t));
+
+ unsigned int i;
+ for (i=0;i<=264;i++) {
+ uint32_t ctlset = ctlsettings[i];
+ /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
+ }
+
+ phy_reset(ddrphyreg, physettings);
+}
+
+static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) {
+ // START register at ddrctl register base offset 0
+ uint32_t regdata = _REG32(0<<2, ahbregaddr);
+ regdata |= 0x1;
+ _REG32(0<<2, ahbregaddr) = regdata;
+ // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210
+ while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {}
+
+ // Disable the BusBlocker in front of the controller AXI slave ports
+ volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr;
+ filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
+ // ^^ RWX + TOR
+}
+
+static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) {
+ // Mask off Bit 8 of Interrupt Status
+ // Bit [8] The MC initialization has been completed
+ _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET);
+}
+
+static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) {
+ // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
+ // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured
+ // Bit [1] A memory access outside the defined PHYSICAL memory space has occured
+ _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET));
+}
+
+static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) {
+ // Mask off Bit 7 of Interrupt Status
+ // Bit [7] An error occured on the port command channel
+ _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET);
+}
+
+static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) {
+ // Mask off Bit 22 of Interrupt Status
+ // Bit [22] The leveling operation has completed
+ _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET);
+}
+
+static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) {
+ _REG32(209<<2, ahbregaddr) = 0x0;
+ size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1;
+ _REG32(210<<2, ahbregaddr) = ((uint32_t) end_addr_16Kblocks);
+ _REG32(212<<2, ahbregaddr) = 0x0;
+ _REG32(214<<2, ahbregaddr) = 0x0;
+ _REG32(216<<2, ahbregaddr) = 0x0;
+ _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
+ _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
+ _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
+ _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
+
+}
+
+static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) {
+ _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET);
+}
+
+static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) {
+ _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET));
+}
+
+static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) {
+ _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET));
+}
+
+static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) {
+ _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET);
+ _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET);
+}
+
+static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) {
+ _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET);
+ _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET);
+}
+
+static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) {
+ _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET);
+}
+
+static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) {
+ return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
+}
+
+static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) {
+ // return bitmask of failed lanes
+
+ size_t ddrphyreg = ahbregaddr + 0x2000;
+
+ uint64_t fails=0;
+ uint32_t slicebase = 0;
+ uint32_t dq = 0;
+
+ // check errata condition
+ for (uint32_t slice = 0; slice < 8; slice++) {
+ uint32_t regbase = slicebase + 34;
+ for (uint32_t reg = 0 ; reg < 4; reg++) {
+ uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg);
+ for (uint32_t bit = 0; bit < 2; bit++) {
+ uint32_t phy_rx_cal_dqn_0_offset;
+
+ if (bit==0) {
+ phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET;
+ }else{
+ phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET;
+ }
+
+ uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
+ uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F;
+
+ uint8_t failc0 = ((down == 0) && (up == 0x3F));
+ uint8_t failc1 = ((up == 0) && (down == 0x3F));
+
+ // print error message on failure
+ if (failc0 || failc1) {
+ //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
+ fails |= (1<<dq);
+ char slicelsc = '0';
+ char slicemsc = '0';
+ slicelsc += (dq % 10);
+ slicemsc += (dq / 10);
+ //uart_puts((void*) UART0_CTRL_ADDR, "S ");
+ //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc);
+ //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc);
+ //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U");
+ //else uart_puts((void*) UART0_CTRL_ADDR, "D");
+ //uart_puts((void*) UART0_CTRL_ADDR, "\n");
+ }
+ dq++;
+ }
+ }
+ slicebase+=128;
+ }
+ return (0);
+}
+
+#endif
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 11:15:01 +0000