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-rw-r--r--src/drivers/intel/gma/gma.h14
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb12
-rw-r--r--src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb15
-rw-r--r--src/mainboard/google/auron/devicetree.cb3
-rw-r--r--src/mainboard/google/auron/variants/auron_paine/overridetree.cb14
-rw-r--r--src/mainboard/google/auron/variants/auron_yuna/overridetree.cb14
-rw-r--r--src/mainboard/google/auron/variants/buddy/overridetree.cb14
-rw-r--r--src/mainboard/google/auron/variants/gandof/overridetree.cb14
-rw-r--r--src/mainboard/google/auron/variants/lulu/overridetree.cb14
-rw-r--r--src/mainboard/google/auron/variants/samus/overridetree.cb14
-rw-r--r--src/mainboard/google/eve/devicetree.cb15
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb15
-rw-r--r--src/mainboard/google/glados/devicetree.cb15
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb14
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb14
-rw-r--r--src/mainboard/google/slippy/devicetree.cb3
-rw-r--r--src/mainboard/google/slippy/variants/falco/overridetree.cb14
-rw-r--r--src/mainboard/google/slippy/variants/leon/overridetree.cb14
-rw-r--r--src/mainboard/google/slippy/variants/peppy/overridetree.cb14
-rw-r--r--src/mainboard/google/slippy/variants/wolf/overridetree.cb14
-rw-r--r--src/mainboard/hp/folio_9480m/devicetree.cb14
-rw-r--r--src/mainboard/lenovo/t440p/devicetree.cb14
-rw-r--r--src/mainboard/purism/librem_bdw/devicetree.cb17
-rw-r--r--src/mainboard/purism/librem_skl/devicetree.cb17
-rw-r--r--src/northbridge/intel/haswell/chip.h15
-rw-r--r--src/northbridge/intel/haswell/gma.c21
-rw-r--r--src/soc/intel/apollolake/chip.h30
-rw-r--r--src/soc/intel/apollolake/graphics.c28
-rw-r--r--src/soc/intel/broadwell/chip.h17
-rw-r--r--src/soc/intel/broadwell/gma.c21
-rw-r--r--src/soc/intel/skylake/chip.h13
-rw-r--r--src/soc/intel/skylake/graphics.c26
32 files changed, 247 insertions, 246 deletions
diff --git a/src/drivers/intel/gma/gma.h b/src/drivers/intel/gma/gma.h
index d7a336c537..ee7d7301c2 100644
--- a/src/drivers/intel/gma/gma.h
+++ b/src/drivers/intel/gma/gma.h
@@ -11,6 +11,20 @@ struct i915_gpu_controller_info {
u32 did[5];
};
+/* Devicetree panel configuration */
+struct i915_gpu_panel_config {
+ unsigned int up_delay_ms;
+ unsigned int down_delay_ms;
+ unsigned int cycle_delay_ms;
+ unsigned int backlight_on_delay_ms;
+ unsigned int backlight_off_delay_ms;
+ unsigned int backlight_pwm_hz;
+ enum {
+ GPU_BACKLIGHT_POLARITY_HIGH = 0,
+ GPU_BACKLIGHT_POLARITY_LOW,
+ } backlight_polarity;
+};
+
#define GMA_STATIC_DISPLAYS(ssc) { \
.use_spread_spectrum_clock = (ssc), \
.ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index b51c73c486..433bc22fbb 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -1,11 +1,13 @@
chip soc/intel/skylake
# Enable Panel as eDP and configure power delays
- register "gpu_pp_up_delay_ms" = "210" # T3
- register "gpu_pp_down_delay_ms" = "500" # T10
- register "gpu_pp_cycle_delay_ms" = "5000" # T12
- register "gpu_pp_backlight_on_delay_ms" = "1" # T7
- register "gpu_pp_backlight_off_delay_ms" = "200" # T9
+ register "panel_cfg" = "{
+ .up_delay_ms = 210, // T3
+ .down_delay_ms = 500, // T10
+ .cycle_delay_ms = 5000, // T12
+ .backlight_on_delay_ms = 1, // T7
+ .backlight_off_delay_ms = 200, // T9
+ }"
# Enable deep Sx states
register "deep_s3_enable_ac" = "1"
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index 808ece0e3d..29f57bd643 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -1,13 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake
- register "gpu_pp_up_delay_ms" = "200" # T3
- register "gpu_pp_down_delay_ms" = " 0" # T10
- register "gpu_pp_cycle_delay_ms" = "500" # T12
- register "gpu_pp_backlight_on_delay_ms" = " 50" # T7
- register "gpu_pp_backlight_off_delay_ms" = " 0" # T9
-
- register "gpu_pch_backlight_pwm_hz" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200, // T3
+ .down_delay_ms = 0, // T10
+ .cycle_delay_ms = 500, // T12
+ .backlight_on_delay_ms = 50, // T7
+ .backlight_off_delay_ms = 0, // T9
+ .backlight_pwm_hz = 200,
+ }"
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 26a53366b4..8bf2c129a4 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -12,9 +12,6 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM value for eDP
- register "gpu_pch_backlight_pwm_hz" = "200"
-
register "s0ix_enable" = "1"
device cpu_cluster 0 on
diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index cb7fb62b34..62e42b1718 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -1,11 +1,13 @@
chip soc/intel/broadwell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "7"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 7,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
chip soc/intel/broadwell/pch
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index 746ec9a58f..174463d0b7 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -1,11 +1,13 @@
chip soc/intel/broadwell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "210"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 210,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
chip soc/intel/broadwell/pch
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 5423043cd8..6762eb42c4 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -1,11 +1,13 @@
chip soc/intel/broadwell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "7"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 7,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
register "s0ix_enable" = "0"
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index 19c0ca0003..ca5d616659 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -1,11 +1,13 @@
chip soc/intel/broadwell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "50"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 50,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
chip soc/intel/broadwell/pch
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index cb7fb62b34..62e42b1718 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -1,11 +1,13 @@
chip soc/intel/broadwell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "7"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 7,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
chip soc/intel/broadwell/pch
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 989b887628..34a785b711 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -3,12 +3,14 @@ chip soc/intel/broadwell
# Enable DDI2 Hotplug with 6ms pulse
register "gpu_dp_c_hotplug" = "0x06"
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "500"
- register "gpu_panel_power_up_delay_ms" = "200"
- register "gpu_panel_power_down_delay_ms" = "50"
- register "gpu_panel_power_backlight_on_delay_ms" = "200"
- register "gpu_panel_power_backlight_off_delay_ms" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 200,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
register "vr_slow_ramp_rate_set" = "3"
register "vr_slow_ramp_rate_enable" = "1"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 0e76de140f..c0531fa238 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -3,13 +3,14 @@ chip soc/intel/skylake
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
- register "gpu_pp_up_delay_ms" = "100"
- register "gpu_pp_down_delay_ms" = "500"
- register "gpu_pp_cycle_delay_ms" = "500"
- register "gpu_pp_backlight_on_delay_ms" = " 1"
- register "gpu_pp_backlight_off_delay_ms" = "200"
-
- register "gpu_pch_backlight_pwm_hz" = "1000"
+ register "panel_cfg" = "{
+ .up_delay_ms = 100,
+ .down_delay_ms = 500,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 1000,
+ }"
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 8c31f9ac70..e9d5a3544a 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -1,12 +1,13 @@
chip soc/intel/skylake
- register "gpu_pp_up_delay_ms" = "200"
- register "gpu_pp_down_delay_ms" = " 50"
- register "gpu_pp_cycle_delay_ms" = "500"
- register "gpu_pp_backlight_on_delay_ms" = " 1"
- register "gpu_pp_backlight_off_delay_ms" = "200"
-
- register "gpu_pch_backlight_pwm_hz" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
# Deep Sx states
register "deep_s3_enable_ac" = "0"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 127334e1ba..5a48c5db47 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -3,13 +3,14 @@ chip soc/intel/skylake
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
- register "gpu_pp_up_delay_ms" = "200"
- register "gpu_pp_down_delay_ms" = " 50"
- register "gpu_pp_cycle_delay_ms" = "500"
- register "gpu_pp_backlight_on_delay_ms" = " 1"
- register "gpu_pp_backlight_off_delay_ms" = "200"
-
- register "gpu_pch_backlight_pwm_hz" = "1000"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 1000,
+ }"
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index a14e927b0f..d3e351ad4f 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -3,12 +3,14 @@ chip soc/intel/skylake
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
- register "gpu_pp_up_delay_ms" = "200"
- register "gpu_pp_down_delay_ms" = "50"
- register "gpu_pp_cycle_delay_ms" = "600"
- register "gpu_pp_backlight_on_delay_ms" = " 1"
- register "gpu_pp_backlight_off_delay_ms" = "200"
- register "gpu_pch_backlight_pwm_hz" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 600,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
# Deep Sx states
register "deep_s3_enable_ac" = "0"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index ff117c8aa2..162b437f32 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -3,12 +3,14 @@ chip soc/intel/skylake
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
- register "gpu_pp_up_delay_ms" = "200"
- register "gpu_pp_down_delay_ms" = "500"
- register "gpu_pp_cycle_delay_ms" = "600"
- register "gpu_pp_backlight_on_delay_ms" = " 1"
- register "gpu_pp_backlight_off_delay_ms" = "200"
- register "gpu_pch_backlight_pwm_hz" = "1000"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 500,
+ .cycle_delay_ms = 600,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 1000,
+ }"
# Deep Sx states
register "deep_s3_enable_ac" = "0"
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index a6fab83a5b..99cae7a406 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -11,9 +11,6 @@ chip northbridge/intel/haswell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM value for eDP
- register "gpu_pch_backlight_pwm_hz" = "200"
-
register "ec_present" = "true"
register "usb_xhci_on_resume" = "true"
diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb
index 54ae6151d2..fc77345dab 100644
--- a/src/mainboard/google/slippy/variants/falco/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb
@@ -1,11 +1,13 @@
chip northbridge/intel/haswell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "60"
- register "gpu_panel_power_down_delay_ms" = "60"
- register "gpu_panel_power_backlight_on_delay_ms" = "210"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 60,
+ .down_delay_ms = 60,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 210,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb
index 9c45f0062b..1d50086c58 100644
--- a/src/mainboard/google/slippy/variants/leon/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb
@@ -1,11 +1,13 @@
chip northbridge/intel/haswell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "210"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 210,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb
index 47edc62397..e732a9270c 100644
--- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb
@@ -1,11 +1,13 @@
chip northbridge/intel/haswell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "400"
- register "gpu_panel_power_up_delay_ms" = "40"
- register "gpu_panel_power_down_delay_ms" = "15"
- register "gpu_panel_power_backlight_on_delay_ms" = "210"
- register "gpu_panel_power_backlight_off_delay_ms" = "210"
+ register "panel_cfg" = "{
+ .up_delay_ms = 40,
+ .down_delay_ms = 15,
+ .cycle_delay_ms = 400,
+ .backlight_on_delay_ms = 210,
+ .backlight_off_delay_ms = 210,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb
index 43bdf561d6..824694720d 100644
--- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb
@@ -1,11 +1,13 @@
chip northbridge/intel/haswell
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "500"
- register "gpu_panel_power_up_delay_ms" = "200"
- register "gpu_panel_power_down_delay_ms" = "50"
- register "gpu_panel_power_backlight_on_delay_ms" = "1"
- register "gpu_panel_power_backlight_off_delay_ms" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
device domain 0 on
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb
index 9baec90d64..712d75e2c4 100644
--- a/src/mainboard/hp/folio_9480m/devicetree.cb
+++ b/src/mainboard/hp/folio_9480m/devicetree.cb
@@ -4,12 +4,14 @@ chip northbridge/intel/haswell
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
- register "gpu_panel_power_backlight_off_delay_ms" = "1"
- register "gpu_panel_power_backlight_on_delay_ms" = "1"
- register "gpu_panel_power_cycle_delay_ms" = "500"
- register "gpu_panel_power_down_delay_ms" = "50"
- register "gpu_panel_power_up_delay_ms" = "200"
- register "gpu_pch_backlight_pwm_hz" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 1,
+ .backlight_pwm_hz = 200,
+ }"
register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on
chip cpu/intel/haswell
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
index e17807f247..fb0442d567 100644
--- a/src/mainboard/lenovo/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -4,12 +4,14 @@ chip northbridge/intel/haswell
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
- register "gpu_panel_power_backlight_off_delay_ms" = "1"
- register "gpu_panel_power_backlight_on_delay_ms" = "1"
- register "gpu_panel_power_cycle_delay_ms" = "500"
- register "gpu_panel_power_down_delay_ms" = "50"
- register "gpu_panel_power_up_delay_ms" = "200"
- register "gpu_pch_backlight_pwm_hz" = "220"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 1,
+ .backlight_pwm_hz = 220,
+ }"
register "ec_present" = "true"
device cpu_cluster 0x0 on
chip cpu/intel/haswell
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index 41943e72ef..cd5bb44b7c 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -6,15 +6,14 @@ chip soc/intel/broadwell
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM value for eDP
- register "gpu_pch_backlight_pwm_hz" = "200"
-
- # Set panel power delays
- register "gpu_panel_power_cycle_delay_ms" = "500"
- register "gpu_panel_power_up_delay_ms" = "200"
- register "gpu_panel_power_down_delay_ms" = "50"
- register "gpu_panel_power_backlight_on_delay_ms" = "200"
- register "gpu_panel_power_backlight_off_delay_ms" = "200"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 200,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index c59df40518..c3a9567ccf 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -1,16 +1,17 @@
chip soc/intel/skylake
- register "gpu_pp_up_delay_ms" = "200"
- register "gpu_pp_down_delay_ms" = " 50"
- register "gpu_pp_cycle_delay_ms" = "500"
- register "gpu_pp_backlight_on_delay_ms" = " 1"
- register "gpu_pp_backlight_off_delay_ms" = "200"
-
- register "gpu_pch_backlight_pwm_hz" = "200"
-
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
+
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index b1c8d37a74..99102b6770 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -3,7 +3,7 @@
#ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H
#define NORTHBRIDGE_INTEL_HASWELL_CHIP_H
-#include <drivers/intel/gma/i915.h>
+#include <drivers/intel/gma/gma.h>
/*
* Digital Port Hotplug Enable:
@@ -17,17 +17,8 @@ struct northbridge_intel_haswell_config {
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u16 gpu_panel_power_cycle_delay_ms; /* T4 time sequence */
- u16 gpu_panel_power_up_delay_ms; /* T1+T2 time sequence */
- u16 gpu_panel_power_down_delay_ms; /* T3 time sequence */
- u16 gpu_panel_power_backlight_on_delay_ms; /* T5 time sequence */
- u16 gpu_panel_power_backlight_off_delay_ms; /* Tx time sequence */
-
- unsigned int gpu_pch_backlight_pwm_hz;
- enum {
- GPU_BACKLIGHT_POLARITY_HIGH = 0,
- GPU_BACKLIGHT_POLARITY_LOW,
- } gpu_pch_backlight_polarity;
+ /* IGD panel configuration */
+ struct i915_gpu_panel_config panel_cfg;
bool gpu_ddi_e_connected;
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 7adcfdaa5c..21053ec1c0 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -243,6 +243,7 @@ static void init_display_planes(void)
static void gma_setup_panel(struct device *dev)
{
struct northbridge_intel_haswell_config *conf = config_of(dev);
+ const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg;
u32 reg32;
/* Setup Digital Port Hotplug */
@@ -257,30 +258,30 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
- reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff;
+ reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_ON_DELAYS, reg32);
}
/* Setup Panel Power Off Delays */
reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) {
- reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff;
+ reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_OFF_DELAYS, reg32);
}
/* Setup Panel Power Cycle Delay */
- if (conf->gpu_panel_power_cycle_delay_ms) {
+ if (panel_cfg->cycle_delay_ms) {
reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0x1f;
- reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f;
+ reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32);
}
/* Enforce the PCH PWM function, as so does Linux.
The CPU PWM controls are disabled after reset. */
- if (conf->gpu_pch_backlight_pwm_hz) {
+ if (panel_cfg->backlight_pwm_hz) {
/* Reference clock is either 24MHz or 135MHz. We can choose
either a 16 or a 128 step increment. Use 16 if we would
have less than 100 steps otherwise. */
@@ -290,7 +291,7 @@ static void gma_setup_panel(struct device *dev)
u32 south_chicken2;
south_chicken2 = gtt_read(SOUTH_CHICKEN2);
- if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+ if (panel_cfg->backlight_pwm_hz > hz_limit) {
pwm_increment = 16;
south_chicken2 |= LPT_PWM_GRANULARITY;
} else {
@@ -299,7 +300,7 @@ static void gma_setup_panel(struct device *dev)
}
gtt_write(SOUTH_CHICKEN2, south_chicken2);
- pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+ pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz;
printk(BIOS_INFO,
"GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n",
refclock / MHz, pwm_increment, pwm_period,
@@ -309,7 +310,7 @@ static void gma_setup_panel(struct device *dev)
gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
gtt_write(BLC_PWM_PCH_CTL1,
- (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
+ (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
}
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 6e4c82d5a4..c94b7ef180 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -4,6 +4,7 @@
#define _SOC_APOLLOLAKE_CHIP_H_
#include <commonlib/helpers.h>
+#include <drivers/intel/gma/gma.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gspi.h>
#include <soc/gpe.h>
@@ -24,22 +25,6 @@ enum pnp_settings {
PNP_PERF_POWER,
};
-struct soc_intel_apl_pp {
- unsigned int up_delay_ms;
- unsigned int down_delay_ms;
- unsigned int cycle_delay_ms;
- unsigned int backlight_on_delay_ms;
- unsigned int backlight_off_delay_ms;
-};
-
-struct soc_intel_apl_blc {
- unsigned int pwm_hz;
- enum {
- GPU_BACKLIGHT_POLARITY_HIGH = 0,
- GPU_BACKLIGHT_POLARITY_LOW,
- } polarity;
-};
-
struct soc_intel_apollolake_config {
/* Common structure containing soc config data required by common code*/
@@ -48,12 +33,13 @@ struct soc_intel_apollolake_config {
/* Common struct containing power limits configuration info */
struct soc_power_limits_config power_limits_config;
- /* IGD panel configuration */
- struct soc_intel_apl_pp gpu_pp[2];
- /* Second backlight control shares logic with other pins (aka. display
- utility pin). Be sure it's used for PWM before setting any value for
- the secondary controls. */
- struct soc_intel_apl_blc gpu_blc[2];
+ /*
+ * IGD panel configuration
+ *
+ * Second backlight control shares logic with other pins (aka. display utility pin).
+ * Be sure it's used for PWM before setting any secondary backlight value.
+ */
+ struct i915_gpu_panel_config panel_cfg[2];
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 4144479fe8..c24ccdfee2 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -11,37 +11,37 @@
#include "chip.h"
static void graphics_configure_panelpower(
- const struct soc_intel_apl_pp *const pp,
+ const struct i915_gpu_panel_config *const panel_cfg,
uint8_t *const mmio, const unsigned int panel_idx)
{
const unsigned int offset = panel_idx * 0x100;
uint32_t reg32;
- reg32 = (DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) << 4 & 0x1f0;
+ reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
reg32 |= PANEL_POWER_RESET;
write32(mmio + PCH_PP_CONTROL + offset, reg32);
- reg32 = pp->up_delay_ms * 10 << 16;
- reg32 |= pp->backlight_on_delay_ms * 10;
+ reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
write32(mmio + PCH_PP_ON_DELAYS + offset, reg32);
- reg32 = pp->down_delay_ms * 10 << 16;
- reg32 |= pp->backlight_off_delay_ms * 10;
+ reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32);
}
static void graphics_configure_backlight(
- const struct soc_intel_apl_blc *const blc,
+ const struct i915_gpu_panel_config *const panel_cfg,
uint8_t *const mmio, const unsigned int panel_idx)
{
- if (!blc->pwm_hz)
+ if (!panel_cfg->backlight_pwm_hz)
return;
- const unsigned int pwm_period = 19200 * 1000 / blc->pwm_hz;
+ const unsigned int pwm_period = 19200 * 1000 / panel_cfg->backlight_pwm_hz;
write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period);
write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2);
write32(mmio + BXT_BLC_PWM_CTL(panel_idx),
- (blc->polarity ? BXT_BLC_PWM_POLARITY : 0));
+ panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0);
/* Second backlight control uses display utility pin. */
if (panel_idx == 1) {
@@ -68,9 +68,9 @@ void graphics_soc_panel_init(struct device *const dev)
return;
mmio = (void *)(uintptr_t)mmio_res->base;
- for (i = 0; i < ARRAY_SIZE(conf->gpu_pp); ++i)
- graphics_configure_panelpower(&conf->gpu_pp[i], mmio, i);
+ for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i)
+ graphics_configure_panelpower(&conf->panel_cfg[i], mmio, i);
- for (i = 0; i < ARRAY_SIZE(conf->gpu_blc); ++i)
- graphics_configure_backlight(&conf->gpu_blc[i], mmio, i);
+ for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i)
+ graphics_configure_backlight(&conf->panel_cfg[i], mmio, i);
}
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index b77cb71f70..9f6c58de47 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -3,7 +3,7 @@
#ifndef _SOC_INTEL_BROADWELL_CHIP_H_
#define _SOC_INTEL_BROADWELL_CHIP_H_
-#include <drivers/intel/gma/i915.h>
+#include <drivers/intel/gma/gma.h>
#include <stdint.h>
struct soc_intel_broadwell_config {
@@ -18,19 +18,8 @@ struct soc_intel_broadwell_config {
u8 gpu_dp_c_hotplug;
u8 gpu_dp_d_hotplug;
- /* Panel power sequence timings */
- u16 gpu_panel_power_cycle_delay_ms;
- u16 gpu_panel_power_up_delay_ms;
- u16 gpu_panel_power_down_delay_ms;
- u16 gpu_panel_power_backlight_on_delay_ms;
- u16 gpu_panel_power_backlight_off_delay_ms;
-
- /* Panel backlight settings */
- unsigned int gpu_pch_backlight_pwm_hz;
- enum {
- GPU_BACKLIGHT_POLARITY_HIGH = 0,
- GPU_BACKLIGHT_POLARITY_LOW,
- } gpu_pch_backlight_polarity;
+ /* IGD panel configuration */
+ struct i915_gpu_panel_config panel_cfg;
/*
* Graphics CD Clock Frequency
diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c
index 9866ed3b39..bbb6678b75 100644
--- a/src/soc/intel/broadwell/gma.c
+++ b/src/soc/intel/broadwell/gma.c
@@ -285,6 +285,7 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
static void gma_setup_panel(struct device *dev)
{
config_t *conf = config_of(dev);
+ const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg;
u32 reg32;
/* Setup Digital Port Hotplug */
@@ -299,30 +300,30 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
- reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff;
+ reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_ON_DELAYS, reg32);
}
/* Setup Panel Power Off Delays */
reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) {
- reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff;
+ reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_OFF_DELAYS, reg32);
}
/* Setup Panel Power Cycle Delay */
- if (conf->gpu_panel_power_cycle_delay_ms) {
+ if (panel_cfg->cycle_delay_ms) {
reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0x1f;
- reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f;
+ reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32);
}
/* So far all devices seem to use the PCH PWM function.
The CPU PWM registers are all zero after reset. */
- if (conf->gpu_pch_backlight_pwm_hz) {
+ if (panel_cfg->backlight_pwm_hz) {
/* For Lynx Point-LP:
Reference clock is 24MHz. We can choose either a 16
or a 128 step increment. Use 16 if we would have less
@@ -333,7 +334,7 @@ static void gma_setup_panel(struct device *dev)
u32 south_chicken2;
south_chicken2 = gtt_read(SOUTH_CHICKEN2);
- if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+ if (panel_cfg->backlight_pwm_hz > hz_limit) {
pwm_increment = 16;
south_chicken2 |= 1 << 5;
} else {
@@ -342,7 +343,7 @@ static void gma_setup_panel(struct device *dev)
}
gtt_write(SOUTH_CHICKEN2, south_chicken2);
- pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+ pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz;
printk(BIOS_INFO,
"GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n",
refclock / MHz, pwm_increment, pwm_period,
@@ -352,7 +353,7 @@ static void gma_setup_panel(struct device *dev)
gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
gtt_write(BLC_PWM_PCH_CTL1,
- (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
+ (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
}
}
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 7d9d93460c..027a2e29e4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -6,7 +6,7 @@
#include <acpi/acpi_device.h>
#include <device/i2c_simple.h>
#include <drivers/i2c/designware/dw_i2c.h>
-#include <drivers/intel/gma/i915.h>
+#include <drivers/intel/gma/gma.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -37,16 +37,7 @@ struct soc_intel_skylake_config {
struct soc_power_limits_config power_limits_config;
/* IGD panel configuration */
- unsigned int gpu_pp_up_delay_ms;
- unsigned int gpu_pp_down_delay_ms;
- unsigned int gpu_pp_cycle_delay_ms;
- unsigned int gpu_pp_backlight_on_delay_ms;
- unsigned int gpu_pp_backlight_off_delay_ms;
- unsigned int gpu_pch_backlight_pwm_hz;
- enum {
- GPU_BACKLIGHT_POLARITY_HIGH = 0,
- GPU_BACKLIGHT_POLARITY_LOW,
- } gpu_pch_backlight_polarity;
+ struct i915_gpu_panel_config panel_cfg;
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form GPP_[A:G] or GPD. */
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 46dc9dbfab..d41c4aa644 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -15,6 +15,7 @@
void graphics_soc_panel_init(struct device *dev)
{
struct soc_intel_skylake_config *conf = config_of(dev);
+ const struct i915_gpu_panel_config *panel_cfg;
struct resource *mmio_res;
uint8_t *base;
u32 reg32;
@@ -22,27 +23,29 @@ void graphics_soc_panel_init(struct device *dev)
if (!conf)
return;
+ panel_cfg = &conf->panel_cfg;
+
mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!mmio_res || !mmio_res->base)
return;
base = (void *)(uintptr_t)mmio_res->base;
- reg32 = conf->gpu_pp_up_delay_ms * 10 << 16;
- reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10;
+ reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
write32(base + PCH_PP_ON_DELAYS, reg32);
- reg32 = conf->gpu_pp_down_delay_ms * 10 << 16;
- reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10;
+ reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
write32(base + PCH_PP_OFF_DELAYS, reg32);
reg32 = read32(base + PCH_PP_DIVISOR);
reg32 &= ~0x1f;
- reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f;
+ reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
write32(base + PCH_PP_DIVISOR, reg32);
/* So far all devices seem to use the PCH PWM function.
The CPU PWM registers are all zero after reset. */
- if (conf->gpu_pch_backlight_pwm_hz) {
+ if (panel_cfg->backlight_pwm_hz) {
/* Reference clock is 24MHz. We can choose either a 16
or a 128 step increment. Use 16 if we would have less
than 100 steps otherwise. */
@@ -51,7 +54,7 @@ void graphics_soc_panel_init(struct device *dev)
u32 south_chicken1;
south_chicken1 = read32(base + SOUTH_CHICKEN1);
- if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+ if (panel_cfg->backlight_pwm_hz > hz_limit) {
pwm_increment = 16;
south_chicken1 &= ~1;
} else {
@@ -60,15 +63,12 @@ void graphics_soc_panel_init(struct device *dev)
}
write32(base + SOUTH_CHICKEN1, south_chicken1);
- pwm_period = 24 * 1000 * 1000 / pwm_increment
- / conf->gpu_pch_backlight_pwm_hz;
+ pwm_period = 24 * 1000 * 1000 / pwm_increment / panel_cfg->backlight_pwm_hz;
/* Start with a 50% duty cycle. */
- write32(base + BLC_PWM_PCH_CTL2,
- pwm_period << 16 | pwm_period / 2);
+ write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
write32(base + BLC_PWM_PCH_CTL1,
- !!conf->gpu_pch_backlight_polarity << 29 |
- BLM_PCH_PWM_ENABLE);
+ !!panel_cfg->backlight_polarity << 29 | BLM_PCH_PWM_ENABLE);
}
}