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-rw-r--r--src/mainboard/biostar/a68n_5200/bootblock.c2
-rw-r--r--src/mainboard/emulation/qemu-q35/bootblock.c4
-rw-r--r--src/mainboard/google/beltino/chromeos.c6
-rw-r--r--src/mainboard/google/jecht/chromeos.c6
-rw-r--r--src/mainboard/google/parrot/chromeos.c2
-rw-r--r--src/mainboard/google/stout/chromeos.c2
-rw-r--r--src/mainboard/samsung/lumpy/chromeos.c8
-rw-r--r--src/mainboard/samsung/stumpy/chromeos.c8
8 files changed, 18 insertions, 20 deletions
diff --git a/src/mainboard/biostar/a68n_5200/bootblock.c b/src/mainboard/biostar/a68n_5200/bootblock.c
index 1d1f0f142b..c289c444de 100644
--- a/src/mainboard/biostar/a68n_5200/bootblock.c
+++ b/src/mainboard/biostar/a68n_5200/bootblock.c
@@ -35,7 +35,7 @@ void bootblock_mainboard_early_init(void)
pm_io_write8(0x24, 1);
/* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
/* enable SIO LPC decode */
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 88be6df891..d8dc02cdc1 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -41,9 +41,7 @@ static void bootblock_northbridge_init(void)
static void enable_spi_prefetch(void)
{
u8 reg8;
- pci_devfn_t dev;
-
- dev = PCI_DEV(0, 0x1f, 0);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, 0xdc);
reg8 &= ~(3 << 2);
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index f3a112d1c7..6c76120813 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -29,20 +29,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index b58b35a31f..90284c564f 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -30,20 +30,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index 818901012b..b1bab25b69 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -15,7 +15,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = {
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 71d7df5685..03796a6c27 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -60,7 +60,7 @@ int get_recovery_mode_switch(void)
if (ec_rec_flag_good)
return ec_in_rec_mode;
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3);
u8 ec_status = ec_read(EC_STATUS_REG);
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 0d5c0f6a07..c306e56080 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -21,7 +21,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
u8 lid = ec_read(0x83);
@@ -44,20 +44,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
if (get_gpio(GPIO_SPI_WP))
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index ac889ec11c..38808dbb14 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -17,7 +17,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = {
@@ -40,20 +40,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))