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-rw-r--r--src/arch/riscv/include/arch/memlayout.h14
-rw-r--r--src/soc/sifive/fu540/include/soc/memlayout.ld5
2 files changed, 17 insertions, 2 deletions
diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h
index 9097cf5721..7baab76479 100644
--- a/src/arch/riscv/include/arch/memlayout.h
+++ b/src/arch/riscv/include/arch/memlayout.h
@@ -20,6 +20,20 @@
#define STACK(addr, size) REGION(stack, addr, size, 4096)
+#if defined(__PRE_RAM__)
+ #define CAR_STACK(addr, size) \
+ REGION(car_stack, addr, size, 4K) \
+ ALIAS_REGION(car_stack, stack)
+ #define MEM_STACK(addr, size) \
+ REGION(mem_stack, addr, size, 4K)
+#else
+ #define CAR_STACK(addr, size) \
+ REGION(car_stack, addr, size, 4K)
+ #define MEM_STACK(addr, size) \
+ REGION(mem_stack, addr, size, 4K) \
+ ALIAS_REGION(mem_stack, stack)
+#endif
+
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld
index a03c03d345..b9b9c479d6 100644
--- a/src/soc/sifive/fu540/include/soc/memlayout.ld
+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld
@@ -25,11 +25,12 @@ SECTIONS
{
L2LIM_START(FU540_L2LIM)
BOOTBLOCK(FU540_L2LIM, 64K)
- STACK(FU540_L2LIM + 64K, 4K)
- PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K)
+ CAR_STACK(FU540_L2LIM + 64K, 20K)
+ PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
ROMSTAGE(FU540_L2LIM + 128K, 128K)
L2LIM_END(FU540_L2LIM + 2M)
DRAM_START(FU540_DRAM)
RAMSTAGE(FU540_DRAM, 256K)
+ MEM_STACK(FU540_DRAM + 256K, 20K)
}