summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c2
-rw-r--r--src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c33
-rw-r--r--src/soc/intel/alderlake/include/soc/meminit.h6
-rw-r--r--src/soc/intel/alderlake/meminit.c1
4 files changed, 31 insertions, 11 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 9d7cc9118f..209ee6a222 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -51,12 +51,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
switch (board_id) {
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
- mupd->FspmConfig.DqPinsInterleaved = 1;
memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated);
break;
case ADL_P_LP4_1:
case ADL_P_LP4_2:
- mupd->FspmConfig.DqPinsInterleaved = 0;
memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated);
break;
default:
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
index f8b366049f..c730b995bc 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
@@ -5,7 +5,21 @@
#include <baseboard/variants.h>
#include <soc/romstage.h>
-static const struct mb_cfg mem_config = {
+static const struct mb_cfg ddr4_mem_config = {
+ /* Baseboard uses only 100ohm Rcomp resistors */
+ .rcomp_resistor = {100, 100, 100},
+
+ /* Baseboard Rcomp target values */
+ .rcomp_targets = {40, 30, 33, 33, 30},
+
+ .dq_pins_interleaved = true,
+
+ .ect = true, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_MOBILE,
+};
+
+static const struct mb_cfg lpddr4_mem_config = {
/* DQ byte map */
.dq_map = {
{ 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */
@@ -33,13 +47,7 @@ static const struct mb_cfg mem_config = {
{ 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }
},
- /* Baseboard uses only 100ohm Rcomp resistors */
- .rcomp_resistor = {100, 100, 100},
-
- /*
- * Baseboard Rcomp target values.
- */
- .rcomp_targets = {40, 30, 33, 33, 30},
+ .dq_pins_interleaved = false,
.ect = true, /* Early Command Training */
@@ -48,5 +56,12 @@ static const struct mb_cfg mem_config = {
const struct mb_cfg *variant_memory_params(void)
{
- return &mem_config;
+ int board_id = get_board_id();
+
+ if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2)
+ return &lpddr4_mem_config;
+ else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2)
+ return &ddr4_mem_config;
+
+ die("unsupported board id : 0x%x\n", board_id);
}
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index 76930be0e7..5fed5680c6 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -77,6 +77,12 @@ struct mb_cfg {
uint16_t rcomp_targets[5];
/*
+ * Dqs Pins Interleaved Setting. Enable/Disable Control
+ * TRUE = enable, FALSE = disable
+ */
+ bool dq_pins_interleaved;
+
+ /*
* Early Command Training Enable/Disable Control
* TRUE = enable, FALSE = disable
*/
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index e7084a5a16..f5f747d79b 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -180,4 +180,5 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg,
mem_cfg->ECT = board_cfg->ect;
mem_cfg->UserBd = board_cfg->UserBd;
+ mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;
}