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-rw-r--r--src/soc/intel/jasperlake/fsp_params.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 28dccabb10..38138be823 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -14,6 +14,18 @@
#include <soc/soc_chip.h>
#include <string.h>
+/*
+ * ME End of Post configuration
+ * 0 - Disable EOP.
+ * 1 - Send in PEI (Applicable for FSP in API mode)
+ * 2 - Send in DXE (Not applicable for FSP in API mode)
+ */
+enum {
+ EOP_DISABLE,
+ EOP_PEI,
+ EOP_DXE,
+} EndOfPost;
+
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
@@ -97,6 +109,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Unlock upper 8 bytes of RTC RAM */
params->RtcMemoryLock = 0;
+ /* Enable End of Post in PEI phase */
+ params->EndOfPostMessage = EOP_PEI;
+
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = 1;