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-rw-r--r--src/mainboard/amd/rumba/chip.h2
-rw-r--r--src/mainboard/amd/rumba/mainboard.c31
-rw-r--r--src/mainboard/olpc/rev_a/Config.lb1
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c28
4 files changed, 52 insertions, 10 deletions
diff --git a/src/mainboard/amd/rumba/chip.h b/src/mainboard/amd/rumba/chip.h
index 90cfe88a93..40efbfa698 100644
--- a/src/mainboard/amd/rumba/chip.h
+++ b/src/mainboard/amd/rumba/chip.h
@@ -1,5 +1,5 @@
extern struct chip_operations mainboard_amd_rumba_ops;
struct mainboard_amd_rumba_config {
- int nothing;
+ int nicirq;
};
diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c
index 133d38fd30..614b87154c 100644
--- a/src/mainboard/amd/rumba/mainboard.c
+++ b/src/mainboard/amd/rumba/mainboard.c
@@ -6,7 +6,38 @@
#include <arch/io.h>
#include "chip.h"
+static void init(struct device *dev) {
+ struct mainboard_amd_rumba_config *mainboard = (struct mainboard_amd_rumba_config*)dev->chip_info;
+ device_t nic = NULL;
+ unsigned bus = 0;
+ unsigned devfn = PCI_DEVFN(0xd, 0);
+ int nicirq = 1;
+
+ if (mainboard->nicirq)
+ nicirq = mainboard->nicirq;
+
+ printk_debug("AMD RUMBA ENTER %s\n", __FUNCTION__);
+
+ if (nicirq) {
+ printk_debug("%s (%x,%x)SET PCI interrupt line to %d\n",
+ __FUNCTION__, bus, devfn, nicirq);
+ nic = dev_find_slot(bus, devfn);
+ if (! nic){
+ printk_err("Could not find NIC\n");
+ } else {
+ pci_write_config8(nic, PCI_INTERRUPT_LINE, nicirq);
+ }
+ }
+ printk_debug("AMD RUMBA EXIT %s\n", __FUNCTION__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
struct chip_operations mainboard_amd_rumba_ops = {
CHIP_NAME("AMD Rumba mainboard ")
+ .enable_dev = enable_dev,
};
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index a7962f51d0..8c5d98388a 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -133,6 +133,7 @@ chip northbridge/amd/gx2
device pci 1.0 on end
device pci 1.1 on end
chip southbridge/amd/cs5536
+ register "enable_gpio0_inta" = "1"
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 0998a6af96..c89e4cb845 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -338,17 +338,27 @@ static void GLPCIInit(void){
}
}
if (gl) {
+ unsigned long pah, pal;
msrnum = gl->desc_name;
msr = rdmsr(msrnum);
-
- /* 20 bit address The bottom 12 bits go into bits 20-31 in eax. The top 8 bits go into 0-7 of edx.*/
- val = msr.hi & 0xff; /* EAX[31:20] = low 12 bits and EAX[7:0] upper 8 bits*/
- val <<= 12; /* EAX[31:20] = junk EAX[19:0] = 20 bit address*/
- val &= 0xfffff;
- val <<= GLPCI_RC_UPPER_TOP_SHIFT;
- msr.hi = val /* Top Set*/;
- msr.lo = (0x100000 >> 12) << GLPCI_RC_LOWER_BASE_SHIFT /* 1MB >> =20bit address then shift into register*/;
- msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
+ /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
+ * translates to a base of 0x00100000 and top of 0xffbf0000
+ * base of 1M and top of around 256M
+ */
+ /* we have to create a page-aligned (4KB page) address for base and top */
+ /* So we need a high page aligned addresss (pah) and low page aligned address (pal)
+ * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
+ */
+ printk_debug("GLPCI r1: system msr.lo 0x%x msr.hi 0x%x\n", msr.lo, msr.hi);
+ pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
+ /* we have the page address. Now make it a page-aligned address */
+ pah <<= 12;
+
+ pal = msr.lo << 12;
+ msr.hi = pah;
+ msr.lo = pal;
+ msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
+ printk_debug("GLPCI r1: system msr.lo 0x%x msr.hi 0x%x\n", msr.lo, msr.hi);
msrnum = GLPCI_RC1;
wrmsr(msrnum, msr);
}