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-rw-r--r--src/arch/i386/boot/acpi.c4
-rw-r--r--src/arch/i386/boot/coreboot_table.c2
-rw-r--r--src/arch/i386/boot/pirq_routing.c14
-rw-r--r--src/arch/i386/boot/tables.c4
-rw-r--r--src/arch/i386/include/arch/acpi.h5
-rw-r--r--src/arch/i386/include/arch/coreboot_tables.h (renamed from src/arch/i386/boot/coreboot_table.h)1
-rw-r--r--src/arch/i386/include/arch/smp/mpspec.h2
-rw-r--r--src/arch/i386/lib/console_printk.c2
-rw-r--r--src/arch/i386/lib/cpu.c2
-rw-r--r--src/boot/hardwaremain.c3
-rw-r--r--src/boot/selfboot.c2
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram_disable.c3
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram_disable.c2
-rw-r--r--src/cpu/x86/car/copy_and_run.c27
-rw-r--r--src/devices/hypertransport.c2
-rw-r--r--src/devices/pci_device.c2
-rw-r--r--src/devices/pnp_device.c20
-rw-r--r--src/devices/root_device.c2
-rw-r--r--src/drivers/generic/debug/debug_dev.c2
-rw-r--r--src/drivers/i2c/adm1026/adm1026.c1
-rw-r--r--src/drivers/i2c/adm1027/adm1027.c1
-rw-r--r--src/include/cpu/cpu.h2
-rw-r--r--src/include/cpu/x86/bist.h2
-rw-r--r--src/include/cpu/x86/lapic.h3
-rw-r--r--src/include/cpu/x86/tsc.h3
-rw-r--r--src/include/delay.h7
-rw-r--r--src/include/device/pnp.h19
-rw-r--r--src/include/device/pnp_def.h4
-rw-r--r--src/include/fallback.h (renamed from src/include/part/fallback_boot.h)6
-rw-r--r--src/include/part/init_timer.h10
-rw-r--r--src/include/reset.h (renamed from src/include/part/hard_reset.h)6
-rw-r--r--src/include/watchdog.h (renamed from src/include/part/watchdog.h)6
-rw-r--r--src/lib/cbmem.c2
-rw-r--r--src/lib/fallback_boot.c4
-rw-r--r--src/lib/ramtest.c16
-rw-r--r--src/mainboard/intel/d945gclf/Kconfig6
-rw-r--r--src/mainboard/intel/d945gclf/acpi_tables.c2
-rw-r--r--src/mainboard/kontron/986lcd-m/Kconfig6
-rw-r--r--src/mainboard/kontron/986lcd-m/acpi_tables.c11
-rw-r--r--src/mainboard/kontron/986lcd-m/devicetree.cb1
-rw-r--r--src/mainboard/kontron/986lcd-m/mainboard.c3
-rw-r--r--src/mainboard/kontron/986lcd-m/mptable.c93
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c8
-rw-r--r--src/mainboard/roda/rk886ex/Kconfig6
-rw-r--r--src/mainboard/roda/rk886ex/acpi_tables.c2
-rw-r--r--src/mainboard/via/epia-m700/acpi_tables.c5
-rw-r--r--src/mainboard/via/epia-m700/wakeup.c1
-rw-r--r--src/northbridge/amd/amdfam10/misc_control.c1
-rw-r--r--src/northbridge/amd/amdk8/misc_control.c2
-rw-r--r--src/northbridge/intel/e7520/pciexp_porta.c2
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta.c2
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta_ep80579.c2
-rw-r--r--src/northbridge/intel/i855pm/i855pm.h0
-rw-r--r--src/northbridge/intel/i945/northbridge.c3
-rw-r--r--src/northbridge/intel/i945/raminit.c12
-rw-r--r--src/northbridge/intel/i945/raminit.h2
-rw-r--r--src/pc80/mc146818rtc_early.c2
-rw-r--r--src/pc80/serial.c2
-rw-r--r--src/pc80/usbdebug_direct_serial.c1
-rw-r--r--src/southbridge/intel/i3100/i3100_pciexp_portb.c2
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h18
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_azalia.c16
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_lpc.c1
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_pci.c19
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_pcie.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_power.h27
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_reset.c1
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_smi.c5
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_smihandler.c1
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c4
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_watchdog.c1
-rw-r--r--src/southbridge/nvidia/ck804/ck804_reset.c2
-rw-r--r--src/southbridge/sis/sis966/sis761.c4
-rw-r--r--src/superio/winbond/w83627thg/superio.c6
75 files changed, 265 insertions, 213 deletions
diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c
index 7a6221a2ef..ee9246993e 100644
--- a/src/arch/i386/boot/acpi.c
+++ b/src/arch/i386/boot/acpi.c
@@ -487,7 +487,7 @@ void suspend_resume(void)
/* this is to be filled by SB code - startup value what was found */
u8 acpi_slp_type = 0;
-int acpi_is_wakeup(void)
+static int acpi_is_wakeup(void)
{
return (acpi_slp_type == 3);
}
@@ -600,7 +600,7 @@ void acpi_jump_to_wakeup(void *vector)
memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
/* copy wakeup trampoline in place */
- memcpy(WAKEUP_BASE, &__wakeup, &__wakeup_size);
+ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
}
diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c
index f3b7f6daca..d956b127a9 100644
--- a/src/arch/i386/boot/coreboot_table.c
+++ b/src/arch/i386/boot/coreboot_table.c
@@ -24,7 +24,7 @@
#include <ip_checksum.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
-#include "coreboot_table.h"
+#include <arch/coreboot_tables.h>
#include <string.h>
#include <version.h>
#include <device/device.h>
diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c
index 0d852c53b9..78e1dd1806 100644
--- a/src/arch/i386/boot/pirq_routing.c
+++ b/src/arch/i386/boot/pirq_routing.c
@@ -3,7 +3,11 @@
#include <string.h>
#include <device/pci.h>
-#if (CONFIG_DEBUG==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+#ifndef CONFIG_IRQ_SLOT_COUNT
+#warning "CONFIG_IRQ_SLOT_COUNT is not defined. PIRQ won't work correctly."
+#endif
+
+#if CONFIG_DEBUG
static void check_pirq_routing_table(struct irq_routing_table *rt)
{
uint8_t *addr = (uint8_t *)rt;
@@ -12,7 +16,6 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
printk_info("Checking Interrupt Routing Table consistency...\n");
-#if defined(CONFIG_IRQ_SLOT_COUNT)
if (sizeof(struct irq_routing_table) != rt->size) {
printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
sizeof(struct irq_routing_table),
@@ -20,7 +23,6 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
);
rt->size=sizeof(struct irq_routing_table);
}
-#endif
for (i = 0; i < rt->size; i++)
sum += addr[i];
@@ -79,11 +81,8 @@ static int verify_copy_pirq_routing_table(unsigned long addr)
return 0;
}
-#else
-#define verify_copy_pirq_routing_table(addr)
#endif
-#if CONFIG_GENERATE_PIRQ_TABLE==1
unsigned long copy_pirq_routing_table(unsigned long addr)
{
/* Align the table to be 16 byte aligned. */
@@ -98,9 +97,8 @@ unsigned long copy_pirq_routing_table(unsigned long addr)
pirq_routing_irqs(addr);
return addr + intel_irq_routing_table.size;
}
-#endif
-#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+#if CONFIG_PIRQ_ROUTE
void pirq_routing_irqs(unsigned long addr)
{
int i, j, k, num_entries;
diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c
index 8000162573..805fe21121 100644
--- a/src/arch/i386/boot/tables.c
+++ b/src/arch/i386/boot/tables.c
@@ -23,12 +23,12 @@
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
#include <arch/pirq_routing.h>
#include <arch/smp/mpspec.h>
#include <arch/acpi.h>
#include <string.h>
#include <cpu/x86/multiboot.h>
-#include "coreboot_table.h"
#include <cbmem.h>
#include <lib.h>
@@ -167,7 +167,7 @@ struct lb_memory *write_tables(void)
acpi_write_rsdp(low_rsdp,
(acpi_rsdt_t *)(high_rsdp->rsdt_address),
- (acpi_xsdt_t *)(high_rsdp->xsdt_address));
+ (acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address));
} else {
printk_err("ERROR: Didn't find RSDP in high table.\n");
}
diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h
index f28a0e97ea..23e4f0d109 100644
--- a/src/arch/i386/include/arch/acpi.h
+++ b/src/arch/i386/include/arch/acpi.h
@@ -355,7 +355,7 @@ typedef struct acpi_ecdt {
} __attribute__ ((packed)) acpi_ecdt_t;
-/* These are implemented by the target port */
+/* These are implemented by the target port or north/southbridge*/
unsigned long write_acpi_tables(unsigned long addr);
unsigned long acpi_fill_madt(unsigned long current);
unsigned long acpi_fill_mcfg(unsigned long current);
@@ -414,7 +414,10 @@ int acpi_get_sleep_type(void);
#endif
+/* northbridge/amd/amdfam10/amdfam10_acpi.c */
unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current);
+/* cpu/intel/speedstep/acpi.c */
+void generate_cpu_entries(void);
#define ACPI_WRITE_MADT_IOAPIC(dev,id) \
do { \
diff --git a/src/arch/i386/boot/coreboot_table.h b/src/arch/i386/include/arch/coreboot_tables.h
index 13ae9a29cb..91e6d6cbd5 100644
--- a/src/arch/i386/boot/coreboot_table.h
+++ b/src/arch/i386/include/arch/coreboot_tables.h
@@ -20,5 +20,6 @@ extern struct cmos_option_table option_table;
/* defined by mainboard.c if the mainboard requires extra resources */
int add_mainboard_resources(struct lb_memory *mem);
+int add_northbridge_resources(struct lb_memory *mem);
#endif /* COREBOOT_TABLE_H */
diff --git a/src/arch/i386/include/arch/smp/mpspec.h b/src/arch/i386/include/arch/smp/mpspec.h
index 2409071af1..ab29f2a088 100644
--- a/src/arch/i386/include/arch/smp/mpspec.h
+++ b/src/arch/i386/include/arch/smp/mpspec.h
@@ -31,6 +31,8 @@ struct intel_mp_floating
unsigned char mpf_checksum; /* Checksum (makes sum 0) */
unsigned char mpf_feature1; /* Standard or configuration ? */
unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
+#define MP_FEATURE_VIRTUALWIRE (1 << 7)
+#define MP_FEATURE_PIC (0 << 7)
unsigned char mpf_feature3; /* Unused (0) */
unsigned char mpf_feature4; /* Unused (0) */
unsigned char mpf_feature5; /* Unused (0) */
diff --git a/src/arch/i386/lib/console_printk.c b/src/arch/i386/lib/console_printk.c
index 694ec9d631..e9005796e9 100644
--- a/src/arch/i386/lib/console_printk.c
+++ b/src/arch/i386/lib/console_printk.c
@@ -1,6 +1,4 @@
-extern int do_printk(int msg_level, const char *fmt, ...);
-
#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
#define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg)
#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg)
diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c
index 247ee88c0c..0bcd5a674c 100644
--- a/src/arch/i386/lib/cpu.c
+++ b/src/arch/i386/lib/cpu.c
@@ -224,7 +224,7 @@ void cpu_initialize(void)
info = cpu_info();
- printk_notice("Initializing CPU #%ld\n", info->index);
+ printk_info("Initializing CPU #%ld\n", info->index);
cpu = info->cpu;
if (!cpu) {
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 071e056892..686b09576f 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -31,8 +31,7 @@ it with the version available from LANL.
#include <device/pci.h>
#include <delay.h>
#include <stdlib.h>
-#include <part/hard_reset.h>
-#include <part/init_timer.h>
+#include <reset.h>
#include <boot/tables.h>
#include <boot/elf.h>
#include <cbfs.h>
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index a26318f97a..09219909a9 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -19,7 +19,7 @@
*/
#include <console/console.h>
-#include <part/fallback_boot.h>
+#include <fallback.h>
#include <boot/elf.h>
#include <boot/elf_boot.h>
#include <boot/coreboot_tables.h>
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index fcdd3f2e19..6dac367c4d 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -54,8 +54,7 @@ void stage1_main(unsigned long bist)
real_main(bist);
/* No servicable parts below this line .. */
-
-#if CAR_DEBUG
+#ifdef CAR_DEBUG
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
index fcdd3f2e19..9af667d655 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
@@ -55,7 +55,7 @@ void stage1_main(unsigned long bist)
/* No servicable parts below this line .. */
-#if CAR_DEBUG
+#ifdef CAR_DEBUG
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c
index 1c109a3c7d..602e77632d 100644
--- a/src/cpu/x86/car/copy_and_run.c
+++ b/src/cpu/x86/car/copy_and_run.c
@@ -1,8 +1,27 @@
-/* Copyright (C) 2009 coresystems GmbH
- (Written by Patrick Georgi <patrick.georgi@coresystems.de> for coresystems GmbH
-*/
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009-2010 coresystems GmbH
+ * Written by Patrick Georgi <patrick.georgi@coresystems.de>
+ * for coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
-void cbfs_and_run_core(char*, unsigned ebp);
+void cbfs_and_run_core(const char *, unsigned ebp);
static void copy_and_run(unsigned cpu_reset)
{
diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c
index 8de20587a8..4bdf4ef8b8 100644
--- a/src/devices/hypertransport.c
+++ b/src/devices/hypertransport.c
@@ -34,8 +34,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
-#include <part/hard_reset.h>
-#include <part/fallback_boot.h>
/* The hypertransport link is already optimized in pre-ram code
* so don't do it again
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 10e6d23048..aeb03c7eee 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -32,8 +32,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <part/hard_reset.h>
-#include <part/fallback_boot.h>
#include <delay.h>
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
#include <device/hypertransport.h>
diff --git a/src/devices/pnp_device.c b/src/devices/pnp_device.c
index 403fa6afe9..6181425673 100644
--- a/src/devices/pnp_device.c
+++ b/src/devices/pnp_device.c
@@ -240,7 +240,25 @@ static void get_resources(device_t dev, struct pnp_info *info)
resource = new_resource(dev, PNP_IDX_DRQ1);
resource->size = 1;
resource->flags |= IORESOURCE_DRQ;
- }
+ }
+ /* These are not IRQs, but set the flag to have the
+ * resource allocator do the right thing
+ */
+ if (info->flags & PNP_EN) {
+ resource = new_resource(dev, PNP_IDX_EN);
+ resource->size = 1;
+ resource->flags |= IORESOURCE_IRQ;
+ }
+ if (info->flags & PNP_MSC0) {
+ resource = new_resource(dev, PNP_IDX_MSC0);
+ resource->size = 1;
+ resource->flags |= IORESOURCE_IRQ;
+ }
+ if (info->flags & PNP_MSC1) {
+ resource = new_resource(dev, PNP_IDX_MSC1);
+ resource->size = 1;
+ resource->flags |= IORESOURCE_IRQ;
+ }
}
void pnp_enable_devices(device_t base_dev, struct device_operations *ops,
diff --git a/src/devices/root_device.c b/src/devices/root_device.c
index b8d56b646b..09582fccf2 100644
--- a/src/devices/root_device.c
+++ b/src/devices/root_device.c
@@ -25,7 +25,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <part/hard_reset.h>
+#include <reset.h>
/**
* Read the resources for the root device,
diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c
index 94ff870fee..bc5b5e6988 100644
--- a/src/drivers/generic/debug/debug_dev.c
+++ b/src/drivers/generic/debug/debug_dev.c
@@ -5,7 +5,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#include <delay.h>
#include "chip.h"
diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c
index 9869100823..ce8181ef3d 100644
--- a/src/drivers/i2c/adm1026/adm1026.c
+++ b/src/drivers/i2c/adm1026/adm1026.c
@@ -4,7 +4,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <cpu/x86/msr.h>
#include "chip.h"
diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c
index 1379bd6ebf..7ce445b32d 100644
--- a/src/drivers/i2c/adm1027/adm1027.c
+++ b/src/drivers/i2c/adm1027/adm1027.c
@@ -4,7 +4,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <cpu/x86/msr.h>
#include "chip.h"
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 053e319d17..b64fd3ce2c 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -17,6 +17,8 @@ void secondary_cpu_init(void);
#if CONFIG_HAVE_SMI_HANDLER
void smm_init(void);
+void smm_lock(void);
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
#endif
#define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h
index 21ea69e67b..c6cd7349fb 100644
--- a/src/include/cpu/x86/bist.h
+++ b/src/include/cpu/x86/bist.h
@@ -1,7 +1,7 @@
#ifndef CPU_X86_BIST_H
#define CPU_X86_BIST_H
-static void report_bist_failure(unsigned long bist)
+static void report_bist_failure(u32 bist)
{
if (bist != 0) {
#if CONFIG_USE_PRINTK_IN_CAR
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 2b77177bbf..de99deebfe 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -60,12 +60,13 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
*/
static inline __attribute__((always_inline)) void stop_this_cpu(void)
{
-
/* Called by an AP when it is ready to halt and wait for a new task */
for(;;) {
hlt();
}
}
+#else
+void stop_this_cpu(void);
#endif
#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 9370adfe00..9177d53818 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -24,9 +24,6 @@ static inline unsigned long long rdtscll(void)
asm volatile ("rdtsc" : "=A" (val));
return val;
}
-
-void init_timer(void);
#endif
-
#endif /* CPU_X86_TSC_H */
diff --git a/src/include/delay.h b/src/include/delay.h
index 175cdaaa29..5d0dc01790 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -1,7 +1,14 @@
#ifndef DELAY_H
#define DELAY_H
+
#if !defined( __ROMCC__)
+#if CONFIG_HAVE_INIT_TIMER == 1
+void init_timer(void);
+#else
+#define init_timer() do{} while(0)
+#endif
+
void udelay(unsigned usecs);
void mdelay(unsigned msecs);
void delay(unsigned secs);
diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h
index 4cf6ff47fb..32e9c5eada 100644
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@@ -33,14 +33,17 @@ struct pnp_info {
struct device_operations *ops;
unsigned function;
unsigned flags;
-#define PNP_IO0 0x01
-#define PNP_IO1 0x02
-#define PNP_IO2 0x04
-#define PNP_IO3 0x08
-#define PNP_IRQ0 0x10
-#define PNP_IRQ1 0x20
-#define PNP_DRQ0 0x40
-#define PNP_DRQ1 0x80
+#define PNP_IO0 0x001
+#define PNP_IO1 0x002
+#define PNP_IO2 0x004
+#define PNP_IO3 0x008
+#define PNP_IRQ0 0x010
+#define PNP_IRQ1 0x020
+#define PNP_DRQ0 0x040
+#define PNP_DRQ1 0x080
+#define PNP_EN 0x100
+#define PNP_MSC0 0x200
+#define PNP_MSC1 0x400
struct io_info io0, io1, io2, io3;
};
struct resource *pnp_get_resource(device_t dev, unsigned index);
diff --git a/src/include/device/pnp_def.h b/src/include/device/pnp_def.h
index b17fde6478..91ec8f2e61 100644
--- a/src/include/device/pnp_def.h
+++ b/src/include/device/pnp_def.h
@@ -1,6 +1,7 @@
#ifndef DEVICE_PNP_DEF_H
#define DEVICE_PNP_DEF_H
+#define PNP_IDX_EN 0x30
#define PNP_IDX_IO0 0x60
#define PNP_IDX_IO1 0x62
#define PNP_IDX_IO2 0x64
@@ -9,6 +10,7 @@
#define PNP_IDX_IRQ1 0x72
#define PNP_IDX_DRQ0 0x74
#define PNP_IDX_DRQ1 0x75
-
+#define PNP_IDX_MSC0 0xf0
+#define PNP_IDX_MSC1 0xf1
#endif /* DEVICE_PNP_DEF_H */
diff --git a/src/include/part/fallback_boot.h b/src/include/fallback.h
index be4e3989bd..baf8684128 100644
--- a/src/include/part/fallback_boot.h
+++ b/src/include/fallback.h
@@ -1,5 +1,5 @@
-#ifndef PART_FALLBACK_BOOT_H
-#define PART_FALLBACK_BOOT_H
+#ifndef FALLBACK_H
+#define FALLBACK_H
#ifndef ASSEMBLY
@@ -15,4 +15,4 @@ void boot_successful(void);
#define RTC_BOOT_BYTE 48
-#endif /* PART_FALLBACK_BOOT_H */
+#endif /* FALLBACK_H */
diff --git a/src/include/part/init_timer.h b/src/include/part/init_timer.h
deleted file mode 100644
index 61142964a2..0000000000
--- a/src/include/part/init_timer.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef PART_INIT_TIMER_H
-#define PART_DELAY_H
-
-#if CONFIG_HAVE_INIT_TIMER == 1
-void init_timer(void);
-#else
-#define init_timer() do{} while(0)
-#endif
-
-#endif /* PART_INIT_TIMER_H */
diff --git a/src/include/part/hard_reset.h b/src/include/reset.h
index cbfc747d1e..fd78189b17 100644
--- a/src/include/part/hard_reset.h
+++ b/src/include/reset.h
@@ -1,11 +1,11 @@
-#ifndef PART_HARD_RESET_H
-#define PART_HARD_RESET_H
+#ifndef RESET_H
+#define RESET_H
#if CONFIG_HAVE_HARD_RESET == 1
void hard_reset(void);
#else
#define hard_reset() do {} while(0)
#endif
-
+void soft_reset(void);
#endif
diff --git a/src/include/part/watchdog.h b/src/include/watchdog.h
index 26b537dbe9..98d6d51865 100644
--- a/src/include/part/watchdog.h
+++ b/src/include/watchdog.h
@@ -1,5 +1,5 @@
-#ifndef PART_WATCHDOG_H
-#define PART_WATCHDOG_H
+#ifndef WATCHDOG_H
+#define WATCHDOG_H
#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
void watchdog_off(void);
@@ -7,4 +7,4 @@ void watchdog_off(void);
#define watchdog_off()
#endif
-#endif /* PART_WATCHDOG_H */
+#endif /* WATCHDOG_H */
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index db761958a9..92a848497d 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -184,7 +184,7 @@ void cbmem_initialize(void)
if (acpi_slp_type == 3) {
if (!cbmem_reinit(high_tables_base)) {
/* Something went wrong, our high memory area got wiped */
- acpi_slp_type == 0;
+ acpi_slp_type = 0;
cbmem_init(high_tables_base, high_tables_size);
}
} else {
diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index b969b6b5cf..e2da65cf91 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -1,6 +1,6 @@
#include <console/console.h>
-#include <part/fallback_boot.h>
-#include <part/watchdog.h>
+#include <fallback.h>
+#include <watchdog.h>
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index 9f329ef51b..4f00030b89 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -30,7 +30,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
* Fill.
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop);
+ printk_debug("DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
#else
print_debug("DRAM fill: ");
print_debug_hex32(start);
@@ -42,7 +42,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
/* Display address being filled */
if (!(addr & 0xfffff)) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x \r", addr);
+ printk_debug("%08lx \r", addr);
#else
print_debug_hex32(addr);
print_debug(" \r");
@@ -52,7 +52,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
};
/* Display final address */
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x\r\nDRAM filled\r\n", addr);
+ printk_debug("%08lx\r\nDRAM filled\r\n", addr);
#else
print_debug_hex32(addr);
print_debug("\r\nDRAM filled\r\n");
@@ -67,7 +67,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
* Verify.
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop);
+ printk_debug("DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
#else
print_debug("DRAM verify: ");
print_debug_hex32(start);
@@ -80,7 +80,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
/* Display address being tested */
if (!(addr & 0xfffff)) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x \r", addr);
+ printk_debug("%08lx \r", addr);
#else
print_debug_hex32(addr);
print_debug(" \r");
@@ -90,7 +90,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
if (value != addr) {
/* Display address with error */
#if CONFIG_USE_PRINTK_IN_CAR
- printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value);
+ printk_err("Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
#else
print_err("Fail: @0x");
print_err_hex32(addr);
@@ -111,7 +111,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
}
/* Display final address */
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x", addr);
+ printk_debug("%08lx", addr);
#else
print_debug_hex32(addr);
#endif
@@ -142,7 +142,7 @@ void ram_check(unsigned long start, unsigned long stop)
* are tested. -Tyson
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop);
+ printk_debug("Testing DRAM : %08lx - %08lx\r\n", start, stop);
#else
print_debug("Testing DRAM : ");
print_debug_hex32(start);
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index c7d567da88..fefeaf6c52 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -91,3 +91,9 @@ config MAX_PHYSICAL_CPUS
int
default 2
depends on BOARD_INTEL_D945GCLF
+
+config HAVE_ACPI_SLIC
+ bool
+ default n
+ depends on BOARD_INTEL_D945GCLF
+
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index 527d708af9..1f8b5299cc 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -35,8 +35,6 @@ extern unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
-unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
#if OLD_ACPI
typedef struct acpi_oemb {
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index c0a01dcc68..e0aab8b590 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -76,3 +76,9 @@ config FALLBACK_VGA_BIOS_FILE
string
default "amipci_01.20"
depends on BOARD_KONTRON_986LCD_M
+
+config HAVE_ACPI_SLIC
+ bool
+ default n
+ depends on BOARD_KONTRON_986LCD_M
+
diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c
index 68f3d9cbf9..cfdd8d07bd 100644
--- a/src/mainboard/kontron/986lcd-m/acpi_tables.c
+++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c
@@ -32,10 +32,9 @@
#include "dmi.h"
extern unsigned char AmlCode[];
-#if HAVE_ACPI_SLIC
+#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
@@ -142,7 +141,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
-#if HAVE_ACPI_SLIC
+#if CONFIG_HAVE_ACPI_SLIC
acpi_header_t *slic;
#endif
acpi_header_t *ssdt;
@@ -216,14 +215,14 @@ unsigned long write_acpi_tables(unsigned long start)
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
- printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
+ printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
break;
}
}
/* And fill it */
- acpi_create_gnvs(current);
+ acpi_create_gnvs((global_nvs_t *)current);
current += 0x100;
ALIGN_CURRENT;
@@ -238,7 +237,7 @@ unsigned long write_acpi_tables(unsigned long start)
printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
-#if HAVE_ACPI_SLIC
+#if CONFIG_HAVE_ACPI_SLIC
printk_debug("ACPI: * SLIC\n");
slic = (acpi_header_t *)current;
current += acpi_create_slic(current);
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index 3b4a5179fb..f1f771ad72 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -102,6 +102,7 @@ chip northbridge/intel/i945
device pnp 4e.3 on # COM4
io 0x60 = 0x2e8
irq 0x70 = 10
+ irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
end
device pnp 4e.5 off # Keyboard
end
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index e45aeb5f2d..2d114df2ef 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -26,10 +26,9 @@
#include <x86emu/x86emu.h>
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
+#include <arch/coreboot_tables.h>
#include "chip.h"
-int add_northbridge_resources(struct lb_memory *mem);
-
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 8f5acb8b59..40cbd79f87 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -27,7 +27,7 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
@@ -36,6 +36,7 @@ void *smp_write_config_table(void *v)
struct device *riser = NULL, *firewire = NULL;
int i;
int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
+ int ioapic_id;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
@@ -86,58 +87,65 @@ void *smp_write_config_table(void *v)
smp_write_bus(mc, isa_bus, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ ioapic_id = 2;
+ smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
/* Legacy Interrupts */
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
/* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
- /* Firewire 4:0.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
+
+ /* Internal PCI bus (Firewire, PCI slot) */
if (firewire) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
}
if (riser) {
/* Old riser card */
// riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
// riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
// riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
/* New Riser Card */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, 0x2, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
}
+ /* PCIe slot */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
+
/* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
@@ -152,9 +160,26 @@ void *smp_write_config_table(void *v)
return smp_next_mpe_entry(mc);
}
+/* MP table generation in coreboot is not very well designed;
+ * One of the issues is that it knows nothing about Virtual
+ * Wire mode, which everyone uses since a decade or so. This
+ * function fixes up our floating table. This spares us doing
+ * a half-baked fix of adding a new parameter to 200+ calls
+ * to smp_write_floating_table()
+ */
+static void fixup_virtual_wire(void *v)
+{
+ struct intel_mp_floating *mf = v;
+
+ mf->mpf_checksum = 0;
+ mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
+ mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
+}
+
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
+ fixup_virtual_wire(v);
return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index e0943ab390..8b9fb0430c 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2007-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -48,6 +48,7 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
+#include <console/console.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/x86/bist.h>
@@ -367,6 +368,8 @@ static void early_ich7_init(void)
//
#include "lib/cbmem.c"
+#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
+
void real_main(unsigned long bist)
{
u32 reg32;
@@ -477,7 +480,7 @@ void real_main(unsigned long bist)
* day.
*/
if (resume_backup_memory)
- memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
@@ -485,4 +488,3 @@ void real_main(unsigned long bist)
#endif
}
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index af5acccacd..1b1aca0fba 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -73,3 +73,9 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x6886
depends on BOARD_RODA_RK886EX
+
+config HAVE_ACPI_SLIC
+ bool
+ default n
+ depends on BOARD_RODA_RK886EX
+
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index afbc80ee53..34faf63e16 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -34,8 +34,6 @@ extern unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
-unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
#define OLD_ACPI 0
#if OLD_ACPI
diff --git a/src/mainboard/via/epia-m700/acpi_tables.c b/src/mainboard/via/epia-m700/acpi_tables.c
index 298dc19c96..4664ec111a 100644
--- a/src/mainboard/via/epia-m700/acpi_tables.c
+++ b/src/mainboard/via/epia-m700/acpi_tables.c
@@ -39,7 +39,6 @@ extern unsigned char AmlCode_dsdt[];
extern unsigned char AmlCode_ssdt[];
extern u32 wake_vec;
-extern u8 acpi_sleep_type;
/*
* These four macros are copied from <arch/smp/mpspec.h>, I have to do this
@@ -203,7 +202,3 @@ unsigned long write_acpi_tables(unsigned long start)
return current;
}
-int acpi_is_wakeup(void)
-{
- return (acpi_sleep_type == 3);
-}
diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c
index 011b680b40..e64fb095d3 100644
--- a/src/mainboard/via/epia-m700/wakeup.c
+++ b/src/mainboard/via/epia-m700/wakeup.c
@@ -31,7 +31,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
-#include <part/init_timer.h> /* for jason_tsc_count_end */
#include "wakeup.h"
int enable_a20(void);
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index a321a656d2..5286529e13 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -30,7 +30,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_10xxx_rev.h>
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index efb44473a4..a1e88aa837 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -14,7 +14,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_fxx_rev.h>
diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c
index ac833cf185..70e58076a7 100644
--- a/src/northbridge/intel/e7520/pciexp_porta.c
+++ b/src/northbridge/intel/e7520/pciexp_porta.c
@@ -6,7 +6,7 @@
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
typedef struct northbridge_intel_e7520_config config_t;
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c
index 8cafb28f38..da010f3703 100644
--- a/src/northbridge/intel/i3100/pciexp_porta.c
+++ b/src/northbridge/intel/i3100/pciexp_porta.c
@@ -28,7 +28,7 @@
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
typedef struct northbridge_intel_i3100_config config_t;
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
index 9fbd5391e1..dbc1b5fdbb 100644
--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -28,7 +28,7 @@
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
typedef struct northbridge_intel_i3100_config config_t;
diff --git a/src/northbridge/intel/i855pm/i855pm.h b/src/northbridge/intel/i855pm/i855pm.h
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/northbridge/intel/i855pm/i855pm.h
+++ /dev/null
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 4ccffc6b55..5f71e19a90 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -31,8 +31,9 @@
#include <boot/tables.h>
#include "chip.h"
#include "i945.h"
+#include <arch/coreboot_tables.h>
-int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(u32 *base, u32 *len)
{
device_t dev;
u32 pciexbar_reg;
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 124ef147c3..be63e7adcc 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -398,12 +398,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
die("No memory installed.\n");
}
- /* The chipset might be able to do this. What the heck, legacy bios
- * just beeps when a single DIMM is in the Channel 1 socket. So let's
- * not bother until someone needs this enough to cope with it.
- */
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n");
+ printk_info("Channel 0 has no memory populated.\n");
}
}
@@ -454,7 +450,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
{
int i, j, idx;
int lowest_common_cas = 0;
- int max_ram_speed;
+ int max_ram_speed = 0;
const u8 ddr2_speeds_table[] = {
0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */
@@ -1593,7 +1589,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo)
if (sysinfo->banks[i] != 8)
continue;
- printk_spew("DIMM%d has 8 banks.\n");
+ printk_spew("DIMM%d has 8 banks.\n", i);
if (i & 1)
MCHBAR16(off32) |= 0x50;
@@ -2572,7 +2568,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
reg8 |= (1 << 2);
pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
-#if C2_SELF_REFRESH_DISABLE
+#ifdef C2_SELF_REFRESH_DISABLE
if (integrated_graphics) {
printk_debug("C2 self-refresh with IGD\n");
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 070b913947..7ebbd7c2c3 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -67,4 +67,6 @@ struct sys_info {
} __attribute__ ((packed));
+void receive_enable_adjust(struct sys_info *sysinfo);
+
#endif /* RAMINIT_H */
diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c
index 6db9ec8e1a..dc601ebd12 100644
--- a/src/pc80/mc146818rtc_early.c
+++ b/src/pc80/mc146818rtc_early.c
@@ -1,5 +1,5 @@
#include <pc80/mc146818rtc.h>
-#include <part/fallback_boot.h>
+#include <fallback.h>
#ifndef CONFIG_MAX_REBOOT_CNT
#error "CONFIG_MAX_REBOOT_CNT not defined"
diff --git a/src/pc80/serial.c b/src/pc80/serial.c
index 6048d8b5bc..cddce333b3 100644
--- a/src/pc80/serial.c
+++ b/src/pc80/serial.c
@@ -1,5 +1,3 @@
-#include <part/fallback_boot.h>
-
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
diff --git a/src/pc80/usbdebug_direct_serial.c b/src/pc80/usbdebug_direct_serial.c
index 21f6109ce3..15eac02306 100644
--- a/src/pc80/usbdebug_direct_serial.c
+++ b/src/pc80/usbdebug_direct_serial.c
@@ -15,7 +15,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
-#include <part/fallback_boot.h>
#include "../lib/usbdebug_direct.c"
static void early_usbdebug_direct_init(void)
diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
index 7fd17188e7..0777a11eb1 100644
--- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c
+++ b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
@@ -28,7 +28,7 @@
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
#define PCIE_LCTL 0x50
#define PCIE_LSTS 0x52
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 9bc0815087..a784a880e4 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -20,4 +20,5 @@
config SOUTHBRIDGE_INTEL_I82801GX
bool
select IOAPIC
+ select USE_WATCHDOG_ON_BOOT
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 1f320c5182..3ae440d568 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -47,6 +47,24 @@
extern void i82801gx_enable(device_t dev);
#endif
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
/* PCI Configuration Space (D31:F0): LPC */
#define SERIRQ_CNTL 0x64
diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
index 2b9b24579b..60b7334c2c 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
@@ -33,7 +33,7 @@
typedef struct southbridge_intel_i82801gx_config config_t;
-static int set_bits(u8 * port, u32 mask, u32 val)
+static int set_bits(u32 port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -62,7 +62,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u8 * base)
+static int codec_detect(u32 base)
{
u32 reg32;
@@ -116,7 +116,7 @@ static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u8 *base)
+static int wait_for_ready(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -139,7 +139,7 @@ static int wait_for_ready(u8 *base)
* is non-operative
*/
-static int wait_for_valid(u8 *base)
+static int wait_for_valid(u32 base)
{
u32 reg32;
@@ -163,7 +163,7 @@ static int wait_for_valid(u8 *base)
return -1;
}
-static void codec_init(struct device *dev, u8 * base, int addr)
+static void codec_init(struct device *dev, u32 base, int addr)
{
u32 reg32;
u32 *verb;
@@ -207,7 +207,7 @@ static void codec_init(struct device *dev, u8 * base, int addr)
printk_debug("Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u8 * base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -218,7 +218,7 @@ static void codecs_init(struct device *dev, u8 * base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u8 *base;
+ u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -303,7 +303,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u8 *) ((u32)res->base);
+ base = (u32)res->base;
printk_debug("Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index be3eee68c5..ccab5482c9 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -27,7 +27,6 @@
#include <pc80/i8259.h>
#include <arch/io.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
#define NMI_OFF 0
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c
index 215563d9c2..d9057cb295 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -22,6 +22,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "i82801gx.h"
static void pci_init(struct device *dev)
{
@@ -34,31 +35,31 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
- pci_write_config8(dev, 0x3c, 0xff);
+ pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, 0x3e);
+ reg16 = pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
reg16 &= ~(1 << 1);
- pci_write_config16(dev, 0x3e, reg16);
+ pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, 0x1b);
+ reg8 = pci_read_config8(dev, SMLT);
reg8 &= 0x07;
reg8 |= (0x04 << 3);
- pci_write_config8(dev, 0x1b, reg8);
+ pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, 0x06);
+ reg16 = pci_read_config16(dev, PSTS);
//reg16 |= 0xf900;
- pci_write_config16(dev, 0x06, reg16);
+ pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, 0x1e);
+ reg16 = pci_read_config16(dev, SECSTS);
// reg16 |= 0xf900;
- pci_write_config16(dev, 0x1e, reg16);
+ pci_write_config16(dev, SECSTS, reg16);
}
#undef PCI_BRIDGE_UPDATE_COMMAND
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
index 67120d6ded..b66a887063 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
@@ -75,7 +75,7 @@ static void pci_init(struct device *dev)
reg16 |= (1 << 6);
pci_write_config16(dev, 0x50, reg16);
-#if EVEN_MORE_DEBUG
+#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
printk_spew(" MBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x24);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_power.h b/src/southbridge/intel/i82801gx/i82801gx_power.h
deleted file mode 100644
index ca72eb2831..0000000000
--- a/src/southbridge/intel/i82801gx/i82801gx_power.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-#define MAINBOARD_POWER_KEEP 2
-
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
diff --git a/src/southbridge/intel/i82801gx/i82801gx_reset.c b/src/southbridge/intel/i82801gx/i82801gx_reset.c
index 35710125b2..29b69ff43a 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_reset.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_reset.c
@@ -19,6 +19,7 @@
*/
#include <arch/io.h>
+#include <reset.h>
void soft_reset(void)
{
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/i82801gx_smi.c
index 7187b1af91..0c70812412 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smi.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_smi.c
@@ -24,6 +24,7 @@
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
@@ -237,7 +238,7 @@ static void smi_set_eos(void)
extern uint8_t smm_relocation_start, smm_relocation_end;
-void smm_relocate(void)
+static void smm_relocate(void)
{
u32 smi_en;
u16 pm1_en;
@@ -317,7 +318,7 @@ void smm_relocate(void)
outb(0x00, 0xb2);
}
-void smm_install(void)
+static void smm_install(void)
{
/* enable the SMM memory window */
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
index cf44772d9f..2717dac2f8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
@@ -27,7 +27,6 @@
#include <cpu/x86/smm.h>
#include <device/pci_def.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
#define DEBUG_SMI
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
index 9edee4faa8..3d61cae9b6 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
@@ -53,8 +53,8 @@ static void usb_ehci_init(struct device *dev)
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
base = res->base;
- reg32 = read32((u8 *)base + 0x24) | (1 << 2);
- write32((u8 *)base + 0x24, reg32);
+ reg32 = read32(base + 0x24) | (1 << 2);
+ write32(base + 0x24, reg32);
/* workaround */
reg8 = pci_read_config8(dev, 0x84);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
index 9304ffc705..38350d7ef2 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
@@ -22,6 +22,7 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <watchdog.h>
void watchdog_off(void)
{
diff --git a/src/southbridge/nvidia/ck804/ck804_reset.c b/src/southbridge/nvidia/ck804/ck804_reset.c
index d9dd95af15..415fdae372 100644
--- a/src/southbridge/nvidia/ck804/ck804_reset.c
+++ b/src/southbridge/nvidia/ck804/ck804_reset.c
@@ -4,7 +4,7 @@
*/
#include <arch/io.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \
(((BUS) & 0xFFF) << 20) | \
diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c
index 090e6e9e21..b4eb48d559 100644
--- a/src/southbridge/sis/sis966/sis761.c
+++ b/src/southbridge/sis/sis966/sis761.c
@@ -34,13 +34,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_fxx_rev.h>
-
-//#include "amdk8.h"
-
#include <arch/io.h>
/**
diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c
index eabce5bb81..bedbea9d6d 100644
--- a/src/superio/winbond/w83627thg/superio.c
+++ b/src/superio/winbond/w83627thg/superio.c
@@ -102,12 +102,12 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, { 0x7f8, 0 }, },
/* No 4 { 0,}, */
- { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
{ &ops, W83627THG_GPIO2,},
- { &ops, W83627THG_GPIO3,},
+ { &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
{ &ops, W83627THG_ACPI, PNP_IRQ0, },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
};