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-rw-r--r--src/soc/intel/cannonlake/chip.h4
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 4f015a71f7..f6ec7ce7cb 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -413,6 +413,10 @@ struct soc_intel_cannonlake_config {
uint8_t LanWakeFromDeepSx;
uint8_t WolEnableOverride;
+#if !CONFIG(SOC_INTEL_COMETLAKE)
+ uint32_t VrPowerDeliveryDesign;
+#endif
+
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index b432087a32..b7e9ad8d8b 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -459,6 +459,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
#endif
}
+#if !CONFIG(SOC_INTEL_COMETLAKE)
+ params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
+#endif
+
dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
params->PeiGraphicsPeimInit = 1;