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-rw-r--r--src/soc/intel/alderlake/bootblock/bootblock.c2
-rw-r--r--src/soc/intel/alderlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/alderlake/include/soc/bootblock.h2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c
index e7d97c50bf..96e6268f74 100644
--- a/src/soc/intel/alderlake/bootblock/bootblock.c
+++ b/src/soc/intel/alderlake/bootblock/bootblock.c
@@ -25,7 +25,7 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
report_platform_info();
- pch_init();
+ bootblock_pch_init();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
tco_configure();
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index 8452d83290..b7d2c15d3c 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -138,7 +138,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc();
}
-void pch_init(void)
+void bootblock_pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 9816b317db..087d29f741 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
/* Bootblock post console init programming */
-void pch_init(void);
+void bootblock_pch_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);