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-rw-r--r--src/soc/intel/skylake/gpio.c3
-rw-r--r--src/soc/intel/skylake/include/soc/gpio.h2
-rw-r--r--src/soc/intel/skylake/include/soc/gpio_defs.h1
3 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 5b9babfde3..6334b3e9bd 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad)
pad_relative = pad - comm->min;
/* DW0 and DW1 regs are 4 bytes each. */
- return &regs[PAD_CFG_DW_OFFSET + pad_relative * 8];
+ return &regs[PAD_CFG_DW_OFFSET + pad_relative *
+ GPIO_DWx_SIZE(GPIO_DWx_COUNT)];
}
static void *gpio_hostsw_reg(gpio_t pad, size_t *bit)
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index dd9b9a340c..75d8abe63a 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -19,6 +19,8 @@
#include <soc/gpio_defs.h>
+#define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x))
+
#define CROS_GPIO_DEVICE_NAME "INT344B:00"
#ifndef __ACPI__
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 112db63e18..42a409bec2 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -33,6 +33,7 @@
#define GPIO_NUM_GROUPS 8
#define GPIO_MAX_NUM_PER_GROUP 24
+#define GPIO_DWx_COUNT 2 /* DW0 and DW1 */
/*
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
*/