diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 10 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 8 |
3 files changed, 23 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 6b6a28f749..244f2ba303 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -68,6 +68,13 @@ struct soc_amd_cezanne_config { uint8_t cppc_epp_max_range; uint8_t cppc_epp_min_range; uint8_t cppc_preferred_cores; + + /* telemetry settings */ + uint32_t telemetry_vddcrvddfull_scale_current_mA; + uint32_t telemetry_vddcrvddoffset; + uint32_t telemetry_vddcrsocfull_scale_current_mA; + uint32_t telemetry_vddcrsocoffset; + }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 2528086977..8da38ffa14 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -118,5 +118,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* S0i3 enable */ mcfg->s0i3_enable = config->s0ix_enable; + /* voltage regulator telemetry settings */ + mcfg->telemetry_vddcrvddfull_scale_current = + config->telemetry_vddcrvddfull_scale_current_mA; + mcfg->telemetry_vddcrvddoffset = + config->telemetry_vddcrvddoffset; + mcfg->telemetry_vddcrsocfull_scale_current = + config->telemetry_vddcrsocfull_scale_current_mA; + mcfg->telemetry_vddcrsocOffset = + config->telemetry_vddcrsocoffset; + fsp_fill_pcie_ddi_descriptors(mcfg); } diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 6e9a1f0969..f01af852d1 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -102,8 +102,12 @@ typedef struct __packed { /** Offset 0x04A4**/ uint8_t fch_ioapic_id; /** Offset 0x04A5**/ uint8_t sata_enable; /** Offset 0x04A6**/ uint8_t fch_reserved[32]; - /** Offset 0x04A7**/ uint8_t s0i3_enable; - /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[57]; + /** Offset 0x04C6**/ uint8_t s0i3_enable; + /** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current; + /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; + /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; + /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; + /** Offset 0x04D7**/ uint8_t UnusedUpdSpace0[41]; /** Offset 0x0500**/ uint16_t UpdTerminator; } FSP_M_CONFIG; |