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-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 802592f4d5..c7ea04bb94 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -30,8 +30,8 @@ SECTIONS
DRAM_START(0x00000000)
/* DMA coherent area: accessed via KSEG1. */
DMA_COHERENT(0x00100000, 1M)
- POSTRAM_CBFS_CACHE(0x00200000, 128K)
- RAMSTAGE(0x00220000, 128K)
+ POSTRAM_CBFS_CACHE(0x00200000, 192K)
+ RAMSTAGE(0x00230000, 128K)
/*
* GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock