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-rw-r--r--src/soc/amd/picasso/Kconfig9
-rw-r--r--src/soc/amd/picasso/southbridge.c3
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 3d699667fe..a42629bdff 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SATA
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+ select PROVIDES_ROM_SHARING
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select PARALLEL_MP
@@ -216,6 +217,14 @@ config PICASSO_LPC_IOMUX
Picasso's LPC bus signals are MUXed with some of the EMMC signals.
Select this option if LPC signals are required.
+config DISABLE_SPI_FLASH_ROM_SHARING
+ def_bool n
+ help
+ Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
+ which indicates a board level ROM transaction request. This
+ removes arbitration with board and assumes the chipset controls
+ the SPI flash bus entirely.
+
config MAINBOARD_POWER_RESTORE
def_bool n
help
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 0d54294543..d742038183 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -360,6 +360,9 @@ void fch_early_init(void)
{
sb_print_pmxc0_status();
i2c_soc_early_init();
+
+ if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+ lpc_disable_spi_rom_sharing();
}
void sb_enable(struct device *dev)