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-rw-r--r--src/vendorcode/amd/Kconfig4
-rw-r--r--src/vendorcode/amd/agesa/Kconfig28
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h68
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h68
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h83
5 files changed, 227 insertions, 24 deletions
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig
index c7f48ac340..23786161d3 100644
--- a/src/vendorcode/amd/Kconfig
+++ b/src/vendorcode/amd/Kconfig
@@ -30,6 +30,10 @@ config CPU_AMD_AGESA_OPENSOURCE
endchoice
+if CPU_AMD_AGESA_OPENSOURCE
+source "src/vendorcode/amd/agesa/Kconfig"
+endif
+
if CPU_AMD_AGESA_BINARY_PI
source "src/vendorcode/amd/pi/Kconfig"
endif
diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig
new file mode 100644
index 0000000000..bfec0457d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# This file is part of the coreboot project.
+
+choice
+ prompt "DDR3 memory profile"
+ default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
+ help
+ Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1.
+ XMP support is experimental, and your PC will fail booting if you choose
+ a profile which does not exist on ANY of your RAM sticks! If in doubt
+ check their SPD Data using a coreboot's great fork of memtest86+ 5.01.
+
+config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
+ bool "JEDEC"
+ help
+ JEDEC memory profile, standard and stable. Is guaranteed to be working.
+
+config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1
+ bool "XMP 1"
+ help
+ XMP 1 memory profile. Check that it exists on ALL of your RAM sticks!
+
+config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2
+ bool "XMP 2"
+ help
+ XMP 2 memory profile. Check that it exists on ALL of your RAM sticks!
+
+endchoice
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h
index 3b37429a66..c7f490df2d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -95,6 +95,8 @@
#define SPD_FTB 9
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC)
+
#define SPD_DIVIDENT 10
#define SPD_DIVISOR 11
@@ -103,18 +105,70 @@
#define SPD_CASHI 15
#define SPD_TAA 16
-#define SPD_TRP 20
-#define SPD_TRRD 19
+#define SPD_TWR 17
#define SPD_TRCD 18
+#define SPD_TRRD 19
+#define SPD_TRP 20
+#define SPD_UPPER_TRC 21 /* bits 7:4 */
+#define SPD_UPPER_TRAS 21 /* bits 3:0 */
#define SPD_TRAS 22
-#define SPD_TWR 17
+#define SPD_TRC 23
#define SPD_TWTR 26
#define SPD_TRTP 27
-#define SPD_TRC 23
-#define SPD_UPPER_TRC 21 /* bit 7:4 */
-#define SPD_UPPER_TRAS 21 /* bit 3:0 */
+#define SPD_UPPER_TFAW 28 /* bits 3:0 */
#define SPD_TFAW 29
-#define SPD_UPPER_TFAW 28 /* bit 3:0 */
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1)
+
+#define SPD_DIVIDENT 180
+#define SPD_DIVISOR 181
+
+#define SPD_TCK 186
+#define SPD_CASLO 188
+#define SPD_CASHI 189
+#define SPD_TAA 187
+
+#define SPD_TWR 193
+#define SPD_TRCD 192
+#define SPD_TRRD 202
+#define SPD_TRP 191
+#define SPD_UPPER_TRC 194 /* bits 7:4 */
+#define SPD_UPPER_TRAS 194 /* bits 3:0 */
+#define SPD_TRAS 195
+#define SPD_TRC 196
+#define SPD_TWTR 205
+#define SPD_TRTP 201
+#define SPD_UPPER_TFAW 203 /* bits 3:0 */
+#define SPD_TFAW 204
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2)
+
+#define SPD_DIVIDENT 182
+#define SPD_DIVISOR 183
+
+#define SPD_TCK 221
+#define SPD_CASLO 223
+#define SPD_CASHI 224
+#define SPD_TAA 222
+
+#define SPD_TWR 228
+#define SPD_TRCD 227
+#define SPD_TRRD 237
+#define SPD_TRP 226
+#define SPD_UPPER_TRC 229 /* bits 7:4 */
+#define SPD_UPPER_TRAS 229 /* bits 3:0 */
+#define SPD_TRAS 230
+#define SPD_TRC 231
+#define SPD_TWTR 240
+#define SPD_TRTP 236
+#define SPD_UPPER_TFAW 238 /* bits 3:0 */
+#define SPD_TFAW 239
+
+#endif
#define SPD_TCK_FTB 34
#define SPD_TAA_FTB 35
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
index ab46e4abbc..bbe5c1238c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -94,6 +94,8 @@
#define SPD_FTB 9
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC)
+
#define SPD_DIVIDENT 10
#define SPD_DIVISOR 11
@@ -102,18 +104,70 @@
#define SPD_CASHI 15
#define SPD_TAA 16
-#define SPD_TRP 20
-#define SPD_TRRD 19
+#define SPD_TWR 17
#define SPD_TRCD 18
+#define SPD_TRRD 19
+#define SPD_TRP 20
+#define SPD_UPPER_TRC 21 /* bits 7:4 */
+#define SPD_UPPER_TRAS 21 /* bits 3:0 */
#define SPD_TRAS 22
-#define SPD_TWR 17
+#define SPD_TRC 23
#define SPD_TWTR 26
#define SPD_TRTP 27
-#define SPD_TRC 23
-#define SPD_UPPER_TRC 21 /* bit 7:4 */
-#define SPD_UPPER_TRAS 21 /* bit 3:0 */
+#define SPD_UPPER_TFAW 28 /* bits 3:0 */
#define SPD_TFAW 29
-#define SPD_UPPER_TFAW 28 /* bit 3:0 */
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1)
+
+#define SPD_DIVIDENT 180
+#define SPD_DIVISOR 181
+
+#define SPD_TCK 186
+#define SPD_CASLO 188
+#define SPD_CASHI 189
+#define SPD_TAA 187
+
+#define SPD_TWR 193
+#define SPD_TRCD 192
+#define SPD_TRRD 202
+#define SPD_TRP 191
+#define SPD_UPPER_TRC 194 /* bits 7:4 */
+#define SPD_UPPER_TRAS 194 /* bits 3:0 */
+#define SPD_TRAS 195
+#define SPD_TRC 196
+#define SPD_TWTR 205
+#define SPD_TRTP 201
+#define SPD_UPPER_TFAW 203 /* bits 3:0 */
+#define SPD_TFAW 204
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2)
+
+#define SPD_DIVIDENT 182
+#define SPD_DIVISOR 183
+
+#define SPD_TCK 221
+#define SPD_CASLO 223
+#define SPD_CASHI 224
+#define SPD_TAA 222
+
+#define SPD_TWR 228
+#define SPD_TRCD 227
+#define SPD_TRRD 237
+#define SPD_TRP 226
+#define SPD_UPPER_TRC 229 /* bits 7:4 */
+#define SPD_UPPER_TRAS 229 /* bits 3:0 */
+#define SPD_TRAS 230
+#define SPD_TRC 231
+#define SPD_TWTR 240
+#define SPD_TRTP 236
+#define SPD_UPPER_TFAW 238 /* bits 3:0 */
+#define SPD_TFAW 239
+
+#endif
#define SPD_TCK_FTB 34
#define SPD_TAA_FTB 35
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h
index bf13c7f13c..bc608a5052 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -95,6 +95,8 @@
#define SPD_FTB 9
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC)
+
#define SPD_DIVIDENT 10
#define SPD_DIVISOR 11
@@ -103,18 +105,82 @@
#define SPD_CASHI 15
#define SPD_TAA 16
-#define SPD_TRP 20
-#define SPD_TRRD 19
+#define SPD_TWR 17
#define SPD_TRCD 18
+#define SPD_TRRD 19
+#define SPD_TRP 20
+#define SPD_UPPER_TRC 21 /* bits 7:4 */
+#define SPD_UPPER_TRAS 21 /* bits 3:0 */
#define SPD_TRAS 22
-#define SPD_TWR 17
+#define SPD_TRC 23
+
+#define SPD_TRFC_LO 24
+#define SPD_TRFC_HI 25
+
#define SPD_TWTR 26
#define SPD_TRTP 27
-#define SPD_TRC 23
-#define SPD_UPPER_TRC 21 /* bit 7:4 */
-#define SPD_UPPER_TRAS 21 /* bit 3:0 */
+#define SPD_UPPER_TFAW 28 /* bits 3:0 */
#define SPD_TFAW 29
-#define SPD_UPPER_TFAW 28 /* bit 3:0 */
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1)
+
+#define SPD_DIVIDENT 180
+#define SPD_DIVISOR 181
+
+#define SPD_TCK 186
+#define SPD_CASLO 188
+#define SPD_CASHI 189
+#define SPD_TAA 187
+
+#define SPD_TWR 193
+#define SPD_TRCD 192
+#define SPD_TRRD 202
+#define SPD_TRP 191
+#define SPD_UPPER_TRC 194 /* bits 7:4 */
+#define SPD_UPPER_TRAS 194 /* bits 3:0 */
+#define SPD_TRAS 195
+#define SPD_TRC 196
+
+#define SPD_TRFC_LO 199
+#define SPD_TRFC_HI 200
+
+#define SPD_TWTR 205
+#define SPD_TRTP 201
+#define SPD_UPPER_TFAW 203 /* bits 3:0 */
+#define SPD_TFAW 204
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2)
+
+#define SPD_DIVIDENT 182
+#define SPD_DIVISOR 183
+
+#define SPD_TCK 221
+#define SPD_CASLO 223
+#define SPD_CASHI 224
+#define SPD_TAA 222
+
+#define SPD_TWR 228
+#define SPD_TRCD 227
+#define SPD_TRRD 237
+#define SPD_TRP 226
+#define SPD_UPPER_TRC 229 /* bits 7:4 */
+#define SPD_UPPER_TRAS 229 /* bits 3:0 */
+#define SPD_TRAS 230
+#define SPD_TRC 231
+
+#define SPD_TRFC_LO 234
+#define SPD_TRFC_HI 235
+
+#define SPD_TWTR 240
+#define SPD_TRTP 236
+#define SPD_UPPER_TFAW 238 /* bits 3:0 */
+#define SPD_TFAW 239
+
+#endif
#define SPD_TCK_FTB 34
#define SPD_TAA_FTB 35
@@ -122,9 +188,6 @@
#define SPD_TRP_FTB 37
#define SPD_TRC_FTB 38
-#define SPD_TRFC_LO 24
-#define SPD_TRFC_HI 25
-
/*-----------------------------
* Jedec DDR II related equates
*-----------------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 19:29:55 +0000