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-rw-r--r--src/mainboard/amd/mahogany/mainboard.c6
-rw-r--r--src/mainboard/amd/mahogany_fam10/mainboard.c7
-rw-r--r--src/mainboard/amd/tilapia_fam10/mainboard.c86
-rw-r--r--src/mainboard/asrock/939a785gmh/mainboard.c7
-rw-r--r--src/southbridge/amd/rs780/rs780_gfx.c36
5 files changed, 138 insertions, 4 deletions
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 0aea2c65ea..0a5f691eae 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -34,7 +34,7 @@ uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
void set_pcie_reset(void);
-
+u8 is_dev3_present(void);
/*
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
@@ -94,6 +94,10 @@ static void get_ide_dma66(void)
}
#endif /* get_ide_dma66 */
+u8 is_dev3_present(void)
+{
+ return 0;
+}
/*************************************************
* enable the dedicated function in mahogany board.
* This function called early than rs780_enable.
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index c877914f86..8ecf4f8d04 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -34,7 +34,7 @@ uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
void set_pcie_reset(void);
-
+u8 is_dev3_present(void);
/*
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
@@ -94,6 +94,11 @@ static void get_ide_dma66(void)
}
#endif /* get_ide_dma66() */
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
/*************************************************
* enable the dedicated function in mahogany board.
* This function called early than rs780_enable.
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index b2b0525503..7bb2b3a1dd 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -48,6 +48,7 @@ uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
void set_pcie_reset(void);
+u8 is_dev3_present(void);
void set_pcie_dereset()
{
@@ -130,6 +131,90 @@ static void get_ide_dma66(void)
#endif
/*
+ * justify the dev3 is exist or not
+ */
+u8 is_dev3_present(void)
+{
+ u16 word;
+ device_t sm_dev;
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* put the GPIO68 output to tristate */
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= 1 << 6;
+ pci_write_config16(sm_dev, 0x7e,word);
+
+ /* read the GPIO68 input status */
+ word = pci_read_config16(sm_dev, 0x7e);
+
+ if(word & (1 << 10)){
+ /*not exist*/
+ return 0;
+ }else{
+ /*exist*/
+ return 1;
+ }
+}
+
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+ u8 byte;
+ u32 dword;
+ device_t sm_dev;
+ /* disable the GPIO40 as CLKREQ2# function */
+ byte = pm_ioread(0xd3);
+ byte &= ~(1 << 7);
+ pm_iowrite(0xd3, byte);
+
+ /* disable the GPIO40 as CLKREQ3# function */
+ byte = pm_ioread(0xd4);
+ byte &= ~(1 << 0);
+ pm_iowrite(0xd4, byte);
+
+ /* enable pull up for GPIO68 */
+ byte = pm2_ioread(0xf1);
+ byte &= ~(1 << 4);
+ pm2_iowrite(0xf1, byte);
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /*if the dev3 is present, set the gfx to 2x8 lanes*/
+ /*otherwise set the gfx to 1x16 lanes*/
+ if(is_dev3_present()){
+
+ printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword |= (1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+
+ }else{
+ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword &= ~(1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+ }
+}
+
+/*
* set thermal config
*/
static void set_thermal_config(void)
@@ -247,6 +332,7 @@ static void tilapia_enable(device_t dev)
set_pcie_dereset();
/* get_ide_dma66(); */
set_thermal_config();
+ set_gpio40_gfx();
}
int add_mainboard_resources(struct lb_memory *mem)
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 0aea2c65ea..9e29546506 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -34,7 +34,7 @@ uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
void set_pcie_reset(void);
-
+u8 is_dev3_present(void);
/*
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
@@ -94,6 +94,11 @@ static void get_ide_dma66(void)
}
#endif /* get_ide_dma66 */
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
/*************************************************
* enable the dedicated function in mahogany board.
* This function called early than rs780_enable.
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
index 88cb935de8..7208acd864 100644
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -35,7 +35,7 @@
#include <delay.h>
#include <cpu/x86/msr.h>
#include "rs780.h"
-
+extern int is_dev3_present(void);
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -1214,6 +1214,40 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
dual_port_configuration(nb_dev, dev);
break;
+
+ case 2:
+
+ if(is_dev3_present()){
+ /* step 1, lane reversal (only need if CMOS option is enabled) */
+ if (cfg->gfx_lane_reversal) {
+ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+ }
+ printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+ /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+ /* AMD calls the configuration CrossFire */
+ set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+ printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+
+ printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+ dual_port_configuration(nb_dev, dev);
+
+ }else{
+ if (cfg->gfx_lane_reversal) {
+ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+ }
+ printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+ printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+ if((dev->path.pci.devfn >> 3) == 2)
+ single_port_configuration(nb_dev, dev);
+ else{
+ set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+ printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
+ }
+ }
+
default:
printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
break;