summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/car/romstage.c4
-rw-r--r--src/cpu/intel/fsp_model_206ax/model_206ax.h4
-rw-r--r--src/cpu/intel/fsp_model_206ax/model_206ax_init.c2
-rw-r--r--src/cpu/intel/fsp_model_406dx/bootblock.c2
-rw-r--r--src/cpu/intel/fsp_model_406dx/model_406dx.h4
-rw-r--r--src/cpu/intel/haswell/haswell.h4
-rw-r--r--src/cpu/intel/haswell/haswell_init.c12
-rw-r--r--src/cpu/intel/haswell/romstage.c4
-rw-r--r--src/cpu/intel/haswell/smmrelocate.c8
-rw-r--r--src/cpu/intel/model_106cx/model_106cx_init.c2
-rw-r--r--src/cpu/intel/model_2065x/model_2065x.h4
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c2
-rw-r--r--src/cpu/intel/model_206ax/model_206ax.h4
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c2
-rw-r--r--src/cpu/intel/model_6ex/model_6ex_init.c2
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c2
-rw-r--r--src/cpu/intel/slot_1/l2_cache.c2
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c8
18 files changed, 37 insertions, 35 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 14f841c08b..0f67c26a8c 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -26,8 +26,8 @@ void * asmlinkage romstage_main(unsigned long bist)
const int num_guards = 4;
const u32 stack_guard = 0xdeadbeef;
u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
- CONFIG_DCACHE_RAM_SIZE -
- DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+ CONFIG_DCACHE_RAM_SIZE -
+ DCACHE_RAM_ROMSTAGE_STACK_SIZE);
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h
index b215f5c7c0..e65b370914 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h
@@ -30,7 +30,7 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL 0x199
+#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -38,7 +38,7 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
+#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index 1b3004c135..e538cb209b 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -177,7 +177,7 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
index 99a27a74af..95eb5090d5 100644
--- a/src/cpu/intel/fsp_model_406dx/bootblock.c
+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c
@@ -61,7 +61,7 @@ static void enable_rom_caching(void)
disable_cache();
set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1,
- CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+ CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
index 805fef11ef..87daeac0ea 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h
@@ -31,7 +31,7 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL 0x199
+#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -39,7 +39,7 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
+#define IA32_MC0_STATUS 0x401
#define MSR_NO_EVICT_MODE 0x2e0
#define MSR_PIC_MSG_CONTROL 0x2e
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 41cd5ba684..2ab299a6d5 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -45,7 +45,7 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL 0x199
+#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -53,7 +53,7 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
+#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 0b243ade9a..d7ff121df4 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -50,7 +50,7 @@
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
- (IRTL_1024_NS >> 10))
+ (IRTL_1024_NS >> 10))
/*
* List of supported C-states in this processor. Only the ULT parts support C8,
@@ -361,7 +361,7 @@ static void configure_pch_power_sharing(void)
pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
- pch_power, pch_power_ext);
+ pch_power, pch_power_ext);
pmsync = RCBA32(PMSYNC_CONFIG);
pmsync2 = RCBA32(PMSYNC_CONFIG2);
@@ -532,19 +532,19 @@ static void configure_c_states(void)
/* C-state Interrupt Response Latency Control 3 - package C8 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
- C_STATE_LATENCY_CONTROL_3_LIMIT;
+ C_STATE_LATENCY_CONTROL_3_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
- C_STATE_LATENCY_CONTROL_4_LIMIT;
+ C_STATE_LATENCY_CONTROL_4_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
- C_STATE_LATENCY_CONTROL_5_LIMIT;
+ C_STATE_LATENCY_CONTROL_5_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
}
@@ -577,7 +577,7 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index c82f3b9831..351c05d87b 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -147,8 +147,8 @@ void * asmlinkage romstage_main(unsigned long bist)
const int num_guards = 4;
const u32 stack_guard = 0xdeadbeef;
u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
- CONFIG_DCACHE_RAM_SIZE -
- CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+ CONFIG_DCACHE_RAM_SIZE -
+ CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
printk(BIOS_DEBUG, "Setting up stack guards.\n");
for (i = 0; i < num_guards; i++)
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 34a35516a7..3ec009ec37 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -221,7 +221,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg)
}
static void fill_in_relocation_params(struct device *dev,
- struct smm_relocation_params *params)
+ struct smm_relocation_params *params)
{
u32 tseg_size;
u32 tsegmb;
@@ -273,7 +273,7 @@ static void fill_in_relocation_params(struct device *dev,
params->uncore_emrr_base.lo = emrr_base;
params->uncore_emrr_base.hi = 0;
params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
- MTRR_PHYS_MASK_VALID;
+ MTRR_PHYS_MASK_VALID;
params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
}
@@ -297,7 +297,9 @@ static void setup_ied_area(struct smm_relocation_params *params)
/* According to the BWG MP init section 2MiB of memory at IEDBASE +
* 2MiB should be zeroed as well. However, I suspect what is intended
- * is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
+ * is to clear the memory covered by EMRR. TODO(adurbin): figure out if
+ * this is really required.
+ */
//memset(ied_base + (2 << 20), 0, (2 << 20));
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 3b9cbdb622..d9ce736787 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -59,7 +59,7 @@ static void configure_misc(void)
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 3); /* TM1 enable */
+ msr.lo |= (1 << 3); /* TM1 enable */
msr.lo |= (1 << 13); /* TM2 enable */
msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 3a581e34f2..8bb3b877e8 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -32,7 +32,7 @@
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_FERR_CAPABILITY 0x1f1
#define FERR_ENABLE (1 << 0)
-#define IA32_PERF_CTL 0x199
+#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -40,7 +40,7 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
+#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 9bc9df1e99..8f1311ec9c 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -176,7 +176,7 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 5fb5c8f9f3..594dde143c 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -30,7 +30,7 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL 0x199
+#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -38,7 +38,7 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
+#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index af712d0db5..ff4fad5e12 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -336,7 +336,7 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index a93b113e0b..84329a1dc1 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -62,7 +62,7 @@ static void configure_misc(void)
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 3); /* TM1 enable */
+ msr.lo |= (1 << 3); /* TM1 enable */
msr.lo |= (1 << 13); /* TM2 enable */
msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 3a6319a62c..653fac8e66 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -65,7 +65,7 @@ static void configure_misc(void)
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 3); /* TM1 enable */
+ msr.lo |= (1 << 3); /* TM1 enable */
msr.lo |= (1 << 13); /* TM2 enable */
msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
index 7c127b3fb0..60b94522af 100644
--- a/src/cpu/intel/slot_1/l2_cache.c
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -692,7 +692,7 @@ int p6_configure_l2_cache(void)
if (v >= 0 && (v & 0x20)) {
bblctl3 = rdmsr(BBL_CR_CTL3);
bblctl3.lo |= (BBLCR3_L2_ADDR_PARITY_ENABLE |
- BBLCR3_L2_CRTN_PARITY_ENABLE);
+ BBLCR3_L2_CRTN_PARITY_ENABLE);
wrmsr(BBL_CR_CTL3, bblctl3);
}
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 7e7f986ccf..2cbe6013cc 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -92,13 +92,13 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
* Since one thread runs at a time during the relocation the save state
* is the same for all cpus. */
save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
- runtime->save_state_size);
+ runtime->save_state_size);
/* The relocated handler runs with all CPUs concurrently. Therefore
* stagger the entry points adjusting SMBASE downwards by save state
* size * CPU num. */
save_state->smbase = relo_params->smram_base -
- cpu * runtime->save_state_size;
+ cpu * runtime->save_state_size;
save_state->iedbase = relo_params->ied_base;
printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
@@ -138,7 +138,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
}
static int install_relocation_handler(int *apic_id_map, int num_cpus,
- struct smm_relocation_params *relo_params)
+ struct smm_relocation_params *relo_params)
{
/* The default SMM entry happens serially at the default location.
* Therefore, there is only 1 concurrent save state area. Set the
@@ -183,7 +183,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
}
static int install_permanent_handler(int *apic_id_map, int num_cpus,
- struct smm_relocation_params *relo_params)
+ struct smm_relocation_params *relo_params)
{
/* There are num_cpus concurrent stacks and num_cpus concurrent save
* state areas. Lastly, set the stack size to the save state size. */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 06:11:36 +0000