summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/aaeon/pfm-540i_revb/romstage.c6
-rw-r--r--src/mainboard/amd/db800/romstage.c6
-rw-r--r--src/mainboard/amd/norwich/romstage.c6
-rw-r--r--src/mainboard/artecgroup/dbe61/romstage.c8
-rw-r--r--src/mainboard/bachmann/ot200/Kconfig6
-rw-r--r--src/mainboard/bachmann/ot200/romstage.c6
-rw-r--r--src/mainboard/digitallogic/msm800sev/romstage.c6
-rw-r--r--src/mainboard/iei/pcisa-lx-800-r10/Kconfig6
-rw-r--r--src/mainboard/iei/pcisa-lx-800-r10/romstage.c10
-rw-r--r--src/mainboard/iei/pm-lx-800-r11/Kconfig19
-rw-r--r--src/mainboard/iei/pm-lx-800-r11/romstage.c12
-rw-r--r--src/mainboard/lippert/hurricane-lx/Kconfig6
-rw-r--r--src/mainboard/lippert/hurricane-lx/romstage.c6
-rw-r--r--src/mainboard/lippert/literunner-lx/Kconfig6
-rw-r--r--src/mainboard/lippert/literunner-lx/romstage.c6
-rw-r--r--src/mainboard/lippert/roadrunner-lx/Kconfig6
-rw-r--r--src/mainboard/lippert/roadrunner-lx/romstage.c6
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Kconfig6
-rw-r--r--src/mainboard/lippert/spacerunner-lx/romstage.c6
-rw-r--r--src/mainboard/pcengines/alix1c/romstage.c6
-rw-r--r--src/mainboard/pcengines/alix2d/romstage.c6
-rw-r--r--src/mainboard/traverse/geos/Kconfig6
-rw-r--r--src/mainboard/traverse/geos/romstage.c6
-rw-r--r--src/mainboard/winent/pl6064/romstage.c6
-rw-r--r--src/northbridge/amd/lx/Kconfig31
-rw-r--r--src/northbridge/amd/lx/pll_reset.c8
26 files changed, 97 insertions, 111 deletions
diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
index 4b510a9f21..2d3b71df6a 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c
+++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
@@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
-#define PLLMSRlo 0x00DE60EE
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -79,7 +75,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 3590c37bfe..2bb6cd379a 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
-#define PLLMSRlo 0x00DE60EE
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -74,7 +70,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index d8fca5a51f..c71b31f2d3 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
-#define PLLMSRlo 0x02000030
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index f97af920c5..61bd03ee2b 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address)
return 0xFF;
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-/* CPU and GLIU mult/div 500/266*/
-#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */
-/* Hold Count - how long we will sit in reset */
-#define PLLMSRlo 0x00DE6000
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -94,7 +88,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig
index a201bdec4b..5d185c0d70 100644
--- a/src/mainboard/bachmann/ot200/Kconfig
+++ b/src/mainboard/bachmann/ot200/Kconfig
@@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select POWER_BUTTON_DEFAULT_DISABLE
select DRIVERS_I2C_IDREG
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT
int
default 6
+config PLLMSRlo
+ hex
+ default 0x07de001e
+
endif # BOARD_BACHMANN_OT200
diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c
index 9edd5f7251..3a8ecad178 100644
--- a/src/mainboard/bachmann/ot200/romstage.c
+++ b/src/mainboard/bachmann/ot200/romstage.c
@@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 1 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */
-#define PLLMSRlo 0x07de001e
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index d30e2b0808..caafd2f3cd 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
-#define PLLMSRlo 0x02000030
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -57,7 +53,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
index eae72aef4d..69e106e750 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT
int
default 9
+config PLLMSRlo
+ hex
+ default 0x00DE6000
+
endif # BOARD_IEI_PCISA_LX_800_R10
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index aec984327a..7bd1b74ba1 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 1 /* Do automatic strapped PLL config */
-//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
-//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
-#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
-//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
-/* Hold Count - how long we will sit in reset */
-#define PLLMSRlo 0x00DE6000
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -78,7 +70,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig
index a897106e68..e443c6c8d6 100644
--- a/src/mainboard/iei/pm-lx-800-r11/Kconfig
+++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig
@@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT
int
default 7
-choice
- prompt "Core/GLIU Frequency"
- default CORE_GLIU_500_266
-
-config CORE_GLIU_500_266
- bool "500MHz / 266MHz"
-
-config CORE_GLIU_500_333
- bool "500MHz / 333MHz"
-
-config CORE_GLIU_500_400
- bool "500MHz / 400MHz"
-
-endchoice
+config PLLMSRlo
+ hex
+ default 0x07de0000
endif # BOARD_IEI_PM_LX_800_R11
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
index f7566221db..2992f53c12 100644
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c
@@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#if CONFIG_CORE_GLIU_500_400
-# define PLLMSRhi 0x0000059c
-#elif CONFIG_CORE_GLIU_500_333
-# define PLLMSRhi 0x0000049c
-#else
-# define PLLMSRhi 0x0000039c
-#endif
-
-#define PLLMSRlo 0x07de000
-
#include <northbridge/amd/lx/raminit.h>
#include <northbridge/amd/lx/pll_reset.c>
#include <northbridge/amd/lx/raminit.c>
@@ -80,7 +70,7 @@ void main(unsigned long bist)
report_bist_failure(bist);
- pll_reset(1);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig
index 118809d333..64e16318c4 100644
--- a/src/mainboard/lippert/hurricane-lx/Kconfig
+++ b/src/mainboard/lippert/hurricane-lx/Kconfig
@@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_333
config MAINBOARD_DIR
string
@@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
+config PLLMSRlo
+ hex
+ default 0x00de6001
+
endif # BOARD_LIPPERT_HURRICANE_LX
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 29aa9d1e4f..b2ee033013 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -40,10 +40,6 @@
/* Bit0 enables Spread Spectrum. */
#define SMC_CONFIG 0x01
-#define ManualConf 1 /* No automatic strapped PLL config */
-#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
-#define PLLMSRlo 0x00DE6001
-
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
@@ -138,7 +134,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig
index 12a3ae145b..c4684c94e2 100644
--- a/src/mainboard/lippert/literunner-lx/Kconfig
+++ b/src/mainboard/lippert/literunner-lx/Kconfig
@@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.
+config PLLMSRlo
+ hex
+ default 0x00de6001
+
endif # BOARD_LIPPERT_LITERUNNER_LX
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 1e82bdb70e..77e2d125f3 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -44,10 +44,6 @@
#define SMC_CONFIG 0x01
#endif
-#define ManualConf 1 /* No automatic strapped PLL config */
-#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
-#define PLLMSRlo 0x00DE6001
-
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
@@ -181,7 +177,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig
index 2d11b33972..f5ec9b9d77 100644
--- a/src/mainboard/lippert/roadrunner-lx/Kconfig
+++ b/src/mainboard/lippert/roadrunner-lx/Kconfig
@@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# SST 49LF008A is possible.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_333
config MAINBOARD_DIR
string
@@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
+config PLLMSRlo
+ hex
+ default 0x00de6001
+
endif # BOARD_LIPPERT_ROADRUNNER_LX
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 20e5b6a1a9..827c41b980 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -37,10 +37,6 @@
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/early_serial.c"
-#define ManualConf 1 /* No automatic strapped PLL config */
-#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
-#define PLLMSRlo 0x00DE6001
-
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
@@ -113,7 +109,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig
index 99ecf7c066..c4a2ce8937 100644
--- a/src/mainboard/lippert/spacerunner-lx/Kconfig
+++ b/src/mainboard/lippert/spacerunner-lx/Kconfig
@@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE
help
If selected, the on-board SSD will act as IDE Slave instead of Master.
+config PLLMSRlo
+ hex
+ default 0x00de6001
+
endif # BOARD_LIPPERT_SPACERUNNER_LX
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 9dcb37b4c9..d62c039513 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -44,10 +44,6 @@
#define SMC_CONFIG 0x01
#endif
-#define ManualConf 1 /* No automatic strapped PLL config */
-#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
-#define PLLMSRlo 0x00DE6001
-
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
@@ -178,7 +174,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index f109031a8c..9de3863bc7 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address)
return spdbytes[address];
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
-#define PLLMSRlo 0x02000030
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -132,7 +128,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 0e8cc63a16..fd5582dc38 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address)
return spdbytes[address];
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
-#define PLLMSRlo 0x02000030
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -156,7 +152,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index 40679fe1f1..3139d7dc1b 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select BOARD_ROMSIZE_KB_1024
select POWER_BUTTON_DEFAULT_DISABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT
int
default 6
+config PLLMSRlo
+ hex
+ default 0x00de602e
+
endif # BOARD_TRAVERSE_GEOS
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 588681bfbb..0b61d41122 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 1 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x0000059C /* manual settings for the PLL */
-#define PLLMSRlo 0x00DE602E
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 6651acd4ca..39e4ecf8b0 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
-#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
-#define PLLMSRlo 0x02000030
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -77,7 +73,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset(ManualConf);
+ pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig
index c1fea495ff..d74d71554a 100644
--- a/src/northbridge/amd/lx/Kconfig
+++ b/src/northbridge/amd/lx/Kconfig
@@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX
bool
select GEODE_VSA
+if NORTHBRIDGE_AMD_LX
+
config VIDEO_MB
int
default 8
- depends on NORTHBRIDGE_AMD_LX
+
+config PLL_MANUAL_CONFIG
+ bool
+
+if PLL_MANUAL_CONFIG
+
+# "Core/GLIU Frequency"
+config CORE_GLIU_500_266
+ bool # "500MHz / 266MHz"
+
+config CORE_GLIU_500_333
+ bool # "500MHz / 333MHz"
+
+config CORE_GLIU_500_400
+ bool # "500MHz / 400MHz"
+
+config PLLMSRhi
+ hex
+ default 0x39c if CORE_GLIU_500_266
+ default 0x49c if CORE_GLIU_500_333
+ default 0x59c if CORE_GLIU_500_400
+
+config PLLMSRlo
+ hex
+
+endif
+
+endif
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 3077b61c9c..bf01e54e29 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-static void pll_reset(char manualconf)
+static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
@@ -31,13 +31,13 @@ static void pll_reset(char manualconf)
if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
printk(BIOS_DEBUG, "Configuring PLL.\n");
- if (manualconf) {
+ if (CONFIG_PLL_MANUAL_CONFIG) {
post_code(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
- msrGlcpSysRstpll.hi = PLLMSRhi;
+ msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi;
/* Hold Count - how long we will sit in reset */
- msrGlcpSysRstpll.lo = PLLMSRlo;
+ msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo;
} else {
/*automatic configuration (straps) */
post_code(POST_PLL_STRAP);