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-rw-r--r--src/soc/intel/cannonlake/smihandler.c40
-rw-r--r--src/soc/intel/common/block/cse/Kconfig8
-rw-r--r--src/soc/intel/common/block/cse/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/cse/disable_heci.c62
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cse.h2
-rw-r--r--src/soc/intel/icelake/smihandler.c40
-rw-r--r--src/soc/intel/tigerlake/smihandler.c40
7 files changed, 76 insertions, 117 deletions
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 550c92dc6f..4be7897f78 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -18,49 +18,11 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/cse.h>
-#include <intelblocks/p2sb.h>
-#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#define CSME0_FBE 0xf
-#define CSME0_BAR 0x0
-#define CSME0_FID 0xb0
-
-static void pch_disable_heci(void)
-{
- struct pcr_sbi_msg msg = {
- .pid = PID_CSME0,
- .offset = 0,
- .opcode = PCR_WRITE,
- .is_posted = false,
- .fast_byte_enable = CSME0_FBE,
- .bar = CSME0_BAR,
- .fid = CSME0_FID
- };
- /* Bit 0: Set to make HECI#1 Function disable */
- uint32_t data32 = 1;
- uint8_t response;
- int status;
-
- /* unhide p2sb device */
- p2sb_unhide();
-
- /* Send SBI command to make HECI#1 function disable */
- status = pcr_execute_sideband_msg(&msg, &data32, &response);
- if (status && response)
- printk(BIOS_ERR, "Fail to make CSME function disable\n");
-
- /* Ensure to Lock SBI interface after this command */
- p2sb_disable_sideband_access();
-
- /* hide p2sb device */
- p2sb_hide();
-}
-
/*
* Specific SOC SMI handler during ramstage finalize phase
*
@@ -75,7 +37,7 @@ void smihandler_soc_at_finalize(void)
config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
- pch_disable_heci();
+ heci_disable();
}
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 321d34ce61..15de0b0536 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -4,3 +4,11 @@ config SOC_INTEL_COMMON_BLOCK_CSE
help
Driver for communication with Converged Security Engine (CSE)
over Host Embedded Controller Interface (HECI)
+
+config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM
+ bool
+ default y if HECI_DISABLE_USING_SMM
+ select SOC_INTEL_COMMON_BLOCK_P2SB
+ help
+ Use this config to include common CSE block to make HECI function
+ disable in SMM mode
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
index 376f00f715..90f76d59b0 100644
--- a/src/soc/intel/common/block/cse/Makefile.inc
+++ b/src/soc/intel/common/block/cse/Makefile.inc
@@ -1,3 +1,4 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c
new file mode 100644
index 0000000000..f560a37e9d
--- /dev/null
+++ b/src/soc/intel/common/block/cse/disable_heci.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Intel Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <string.h>
+
+#define CSME0_FBE 0xf
+#define CSME0_BAR 0x0
+#define CSME0_FID 0xb0
+
+/* Disable HECI using Sideband interface communication */
+void heci_disable(void)
+{
+ struct pcr_sbi_msg msg = {
+ .pid = PID_CSME0,
+ .offset = 0,
+ .opcode = PCR_WRITE,
+ .is_posted = false,
+ .fast_byte_enable = CSME0_FBE,
+ .bar = CSME0_BAR,
+ .fid = CSME0_FID
+ };
+ /* Bit 0: Set to make HECI#1 Function disable */
+ uint32_t data32 = 1;
+ uint8_t response;
+ int status;
+
+ /* unhide p2sb device */
+ p2sb_unhide();
+
+ /* Send SBI command to make HECI#1 function disable */
+ status = pcr_execute_sideband_msg(&msg, &data32, &response);
+ if (status || response)
+ printk(BIOS_ERR, "Fail to make CSME function disable\n");
+
+ /* Ensure to Lock SBI interface after this command */
+ p2sb_disable_sideband_access();
+
+ /* hide p2sb device */
+ p2sb_hide();
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index c597a3f46f..59ddc5b5d5 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -97,6 +97,8 @@ int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t
* Returns 0 on failure and 1 on success.
*/
int heci_reset(void);
+/* Disable HECI using Sideband interface communication */
+void heci_disable(void);
/* Reads config value from a specified offset in the CSE PCI Config space. */
uint32_t me_read_config32(int offset);
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index 5228f5d4a0..6be7b70338 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -16,49 +16,11 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/cse.h>
-#include <intelblocks/p2sb.h>
-#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#define CSME0_FBE 0xf
-#define CSME0_BAR 0x0
-#define CSME0_FID 0xb0
-
-static void pch_disable_heci(void)
-{
- struct pcr_sbi_msg msg = {
- .pid = PID_CSME0,
- .offset = 0,
- .opcode = PCR_WRITE,
- .is_posted = false,
- .fast_byte_enable = CSME0_FBE,
- .bar = CSME0_BAR,
- .fid = CSME0_FID
- };
- /* Bit 0: Set to make HECI#1 Function disable */
- uint32_t data32 = 1;
- uint8_t response;
- int status;
-
- /* unhide p2sb device */
- p2sb_unhide();
-
- /* Send SBI command to make HECI#1 function disable */
- status = pcr_execute_sideband_msg(&msg, &data32, &response);
- if (status && response)
- printk(BIOS_ERR, "Fail to make CSME function disable\n");
-
- /* Ensure to Lock SBI interface after this command */
- p2sb_disable_sideband_access();
-
- /* hide p2sb device */
- p2sb_hide();
-}
-
/*
* Specific SOC SMI handler during ramstage finalize phase
*
@@ -73,7 +35,7 @@ void smihandler_soc_at_finalize(void)
config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
- pch_disable_heci();
+ heci_disable();
}
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index 68954eb999..0e8d345bac 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -16,49 +16,11 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/cse.h>
-#include <intelblocks/p2sb.h>
-#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#define CSME0_FBE 0xf
-#define CSME0_BAR 0x0
-#define CSME0_FID 0xb0
-
-static void pch_disable_heci(void)
-{
- struct pcr_sbi_msg msg = {
- .pid = PID_CSME0,
- .offset = 0,
- .opcode = PCR_WRITE,
- .is_posted = false,
- .fast_byte_enable = CSME0_FBE,
- .bar = CSME0_BAR,
- .fid = CSME0_FID
- };
- /* Bit 0: Set to make HECI#1 Function disable */
- uint32_t data32 = 1;
- uint8_t response;
- int status;
-
- /* unhide p2sb device */
- p2sb_unhide();
-
- /* Send SBI command to make HECI#1 function disable */
- status = pcr_execute_sideband_msg(&msg, &data32, &response);
- if (status && response)
- printk(BIOS_ERR, "Fail to make CSME function disable\n");
-
- /* Ensure to Lock SBI interface after this command */
- p2sb_disable_sideband_access();
-
- /* hide p2sb device */
- p2sb_hide();
-}
-
/*
* Specific SOC SMI handler during ramstage finalize phase
*
@@ -73,7 +35,7 @@ void smihandler_soc_at_finalize(void)
config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
- pch_disable_heci();
+ heci_disable();
}
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 06:33:08 +0000