summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/pi/hudson/early_setup.c4
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.c5
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.h2
-rw-r--r--src/southbridge/amd/pi/hudson/lpc.c12
-rw-r--r--src/southbridge/amd/pi/hudson/sm.c12
5 files changed, 18 insertions, 17 deletions
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index ae8b406ad6..d95385be1e 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -276,7 +276,7 @@ void hudson_clk_output_48Mhz(void)
static uintptr_t hudson_spibase(void)
{
/* Make sure the base address is predictable */
- device_t dev = PCI_DEV(0, 0x14, 3);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)
& 0xfffffff0;
@@ -328,7 +328,7 @@ void hudson_read_mode(u32 mode)
void hudson_tpm_decode_spi(void)
{
- device_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */
u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c
index e306836736..a1c805dea1 100644
--- a/src/southbridge/amd/pi/hudson/hudson.c
+++ b/src/southbridge/amd/pi/hudson/hudson.c
@@ -55,14 +55,15 @@ u16 pm_read16(u16 reg)
return read16((void *)(PM_MMIO_BASE + reg));
}
-void hudson_enable(device_t dev)
+void hudson_enable(struct device *dev)
{
printk(BIOS_DEBUG, "hudson_enable()\n");
switch (dev->path.pci.devfn) {
case (0x14 << 3) | 7: /* 0:14.7 SD */
if (dev->enabled == 0) {
// read the VENDEV ID
- device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7));
+ struct device *sd_dev =
+ dev_find_slot( 0, PCI_DEVFN( 0x14, 7));
u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16;
/* turn off the SDHC controller in the PM reg */
u8 reg8;
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 2ccd485b68..091464f14d 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -197,7 +197,7 @@ void configure_hudson_uart(void);
#endif
#else
-void hudson_enable(device_t dev);
+void hudson_enable(struct device *dev);
void s3_resume_init_data(void *FchParams);
#endif /* __PRE_RAM__ */
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index da51cd042d..587fd95b27 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -31,11 +31,11 @@
#include "hudson.h"
#include "pci_devs.h"
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
{
u8 byte;
u32 dword;
- device_t sm_dev;
+ struct device *sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -93,7 +93,7 @@ static void lpc_init(device_t dev)
pm_write8(PM_SERIRQ_CONF, byte);
}
-static void hudson_lpc_read_resources(device_t dev)
+static void hudson_lpc_read_resources(struct device *dev)
{
struct resource *res;
@@ -144,7 +144,7 @@ static void hudson_lpc_set_resources(struct device *dev)
* @param dev the device whose children's resources are to be enabled
*
*/
-static void hudson_lpc_enable_childrens_resources(device_t dev)
+static void hudson_lpc_enable_childrens_resources(struct device *dev)
{
struct bus *link;
u32 reg, reg_x;
@@ -184,7 +184,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev)
reg_var[0] = pci_read_config16(dev, 0x64);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device *child;
for (child = link->children; child;
child = child->sibling) {
if (child->enabled
@@ -323,7 +323,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev)
pci_write_config8(dev, 0x74, wiosize);
}
-static void hudson_lpc_enable_resources(device_t dev)
+static void hudson_lpc_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
hudson_lpc_enable_childrens_resources(dev);
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index db29d10dd1..b3691555d2 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -41,12 +41,12 @@
* HUDSON enables SATA by default in SMBUS Control.
*/
-static void sm_init(device_t dev)
+static void sm_init(struct device *dev)
{
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
}
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device *dev)
{
u32 device;
struct resource *res;
@@ -60,7 +60,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device *dev, u8 val)
{
u32 device;
struct resource *res;
@@ -74,7 +74,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u32 device;
struct resource *res;
@@ -88,7 +88,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u32 device;
struct resource *res;
@@ -108,7 +108,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
-static void hudson_sm_read_resources(device_t dev)
+static void hudson_sm_read_resources(struct device *dev)
{
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 05:29:05 +0000