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-rw-r--r--src/soc/intel/baytrail/include/soc/pmc.h4
-rw-r--r--src/soc/intel/baytrail/smm.c3
-rw-r--r--src/soc/intel/braswell/include/soc/pm.h4
-rw-r--r--src/soc/intel/braswell/smm.c3
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pmc.h10
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/pmc.h4
-rw-r--r--src/soc/intel/fsp_baytrail/smm.c3
7 files changed, 6 insertions, 25 deletions
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index 09d13221b3..6cdf419042 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -281,11 +281,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
-#if CONFIG(ELOG)
void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
/* Return non-zero when RTC failure happened. */
int rtc_failure(void);
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 4f019229e4..9f10f70b61 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -38,7 +38,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
- southcluster_log_state();
+ if (CONFIG(ELOG))
+ southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 5063342955..744fcf085f 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -242,11 +242,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
-#if CONFIG(ELOG)
void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
/* Return non-zero when RTC failure happened. */
int rtc_failure(void);
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c
index 364cda5b5a..c108a3629e 100644
--- a/src/soc/intel/braswell/smm.c
+++ b/src/soc/intel/braswell/smm.c
@@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
- southcluster_log_state();
+ if (CONFIG(ELOG))
+ southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());
diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h
index af840a2f1a..62201d97a7 100644
--- a/src/soc/intel/denverton_ns/include/soc/pmc.h
+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h
@@ -262,14 +262,4 @@
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
-
-#if CONFIG(ELOG)
-void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
-
-#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
-
#endif /* _DENVERTON_NS_PMC_H_ */
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
index 71c8e10446..9e588addae 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
@@ -285,11 +285,7 @@ void disable_all_gpe(void);
uint32_t chipset_prev_sleep_state(uint32_t clear);
-#if CONFIG(ELOG)
void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index 0c40429aae..fbfd094c93 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -40,7 +40,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
- southcluster_log_state();
+ if (CONFIG(ELOG))
+ southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());