6 files changed, 76 insertions, 2 deletions
diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
index c35d0b3876..e8e5cd6f90 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
@@ -19,6 +19,7 @@
 #include <romstage_handoff.h>
 #include <soc/sdram.h>
 #include <soc/timer.h>
+#include <soc/mmu.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <program_loading.h>
@@ -37,6 +38,7 @@ void main(void)
 	bdk_config_set_fdt(devtree);
 
 	sdram_init();
+	soc_mmu_init();
 
 	watchdog_poke(0);
 
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index d265c19bb8..2e12b0137c 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -42,6 +42,8 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c
 romstage-< += cpu.c
 
 romstage-y += sdram.c
+romstage-y += mmu.c
+
 romstage-y += ../common/cbmem.c
 # BDK coreboot interface
 romstage-y += ../common/bdk-coreboot.c
diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h
index e23549450b..8c993ad9d2 100644
--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h
+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h
@@ -23,6 +23,10 @@
 /* ARM code entry vector */
 #define BOOTROM_OFFSET		0x100000
 
+/* Start of IO space */
+#define IO_SPACE_START		0x800000000000ULL
+#define IO_SPACE_SIZE		0x100000000000ULL
+
 /* L2C */
 #define L2C_PF_BAR0		0x87E080800000ULL
 #define L2C_TAD0_PF_BAR0	(0x87E050000000ULL + 0x10000)
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index f0ac2c9da5..d7ee5766a0 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -33,8 +33,8 @@ SECTIONS
 	BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
 	ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
 	SRAM_END(BOOTROM_OFFSET + 0x80000)
-	TTB(BOOTROM_OFFSET + 0x80000, 128K)
-	RAMSTAGE(BOOTROM_OFFSET + 0xa0000, 512K)
+	TTB(BOOTROM_OFFSET + 0x80000, 512K)
+	RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)
 
 	/* Leave some space for the payload */
 	POSTRAM_CBFS_CACHE(0x2000000, 16M)
diff --git a/src/soc/cavium/cn81xx/include/soc/mmu.h b/src/soc/cavium/cn81xx/include/soc/mmu.h
new file mode 100644
index 0000000000..9b811c3966
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/mmu.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H
+#define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H
+
+void soc_mmu_init(void);
+
+#endif  /* ! __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H */
diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c
new file mode 100644
index 0000000000..d6e7ac5ee1
--- /dev/null
+++ b/src/soc/cavium/cn81xx/mmu.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015         MediaTek Inc.
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <soc/addressmap.h>
+#include <soc/mmu.h>
+#include <soc/sdram.h>
+#include <arch/mmu.h>
+
+void soc_mmu_init(void)
+{
+	const unsigned long devmem = MA_DEV | MA_S | MA_RW;
+	const unsigned long secure_mem = MA_MEM | MA_S | MA_RW;
+
+	mmu_init();
+
+	/*
+	 * Need to use secure mem attribute, as firmware is running in ARM TZ
+	 * region.
+	 */
+	mmu_config_range((void *)_ttb, _ttb_size, secure_mem);
+	mmu_config_range((void *)_dram, sdram_size_mb() * MiB, secure_mem);
+	/* IO space has the MSB set and is divided into 4 sub-regions:
+	 * * NCB
+	 * * SLI
+	 * * RSL
+	 * * AP
+	 */
+	mmu_config_range((void *)IO_SPACE_START, IO_SPACE_SIZE, devmem);
+
+	mmu_enable();
+}