diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/agesa/Kconfig | 8 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/common/agesa-entry-cfg.h | 4 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 4605dd3ba9..602a9b0528 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -72,6 +72,14 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config ENABLE_MRC_CACHE + bool "Use cached memory configuration" + default n + select SPI_FLASH + help + Try to restore memory training results + from non-volatile memory. + config S3_DATA_POS hex default 0xFFFF0000 diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h index 0f72fe8c51..6602c99d49 100644 --- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -24,7 +24,9 @@ #define AGESA_ENTRY_INIT_MID TRUE #define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#define AGESA_ENTRY_INIT_S3SAVE \ + (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) || \ + IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) #endif |