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-rw-r--r--src/Kconfig7
-rw-r--r--src/drivers/Kconfig1
-rw-r--r--src/drivers/Makefile.inc1
-rw-r--r--src/drivers/spi/Kconfig81
-rw-r--r--src/drivers/spi/Makefile.inc12
-rw-r--r--src/drivers/spi/eon.c161
-rw-r--r--src/drivers/spi/macronix.c220
-rw-r--r--src/drivers/spi/spansion.c241
-rw-r--r--src/drivers/spi/spi_flash.c309
-rw-r--r--src/drivers/spi/spi_flash_internal.h81
-rw-r--r--src/drivers/spi/sst.c268
-rw-r--r--src/drivers/spi/stmicro.c250
-rw-r--r--src/drivers/spi/winbond.c218
-rw-r--r--src/include/device/pci_ids.h4
-rw-r--r--src/include/spi.h203
-rw-r--r--src/include/spi_flash.h91
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig2
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc2
-rw-r--r--src/southbridge/intel/bd82x6x/spi.c699
19 files changed, 2851 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig
index a6b09dc156..a5a0f0077e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -946,6 +946,13 @@ config DEBUG_TPM
help
This option enables additional TPM related debug messages.
+config DEBUG_SPI_FLASH
+ bool "Output verbose SPI flash debug messages"
+ default n
+ depends on SPI_FLASH
+ help
+ This option enables additional SPI flash related debug messages.
+
if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
# Only visible with the right southbridge and loglevel.
config DEBUG_INTEL_ME
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 259bc290a6..60e5b65140 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -26,3 +26,4 @@ source src/drivers/oxford/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/trident/Kconfig
source src/drivers/ics/Kconfig
+source src/drivers/spi/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 5f6dadfcc5..851a4dfdbe 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -26,4 +26,5 @@ subdirs-y += oxford
subdirs-y += sil
subdirs-y += trident
subdirs-y += ics
+subdirs-y += spi
subdirs-$(CONFIG_ARCH_X86) += pc80
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
new file mode 100644
index 0000000000..ee7584c0c4
--- /dev/null
+++ b/src/drivers/spi/Kconfig
@@ -0,0 +1,81 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 The Chromium OS Authors.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SPI_FLASH
+ bool
+ default n
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash.
+
+config SPI_FLASH_EON
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by EON.
+
+config SPI_FLASH_MACRONIX
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by Macronix.
+
+config SPI_FLASH_SPANSION
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by Spansion.
+
+config SPI_FLASH_SST
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by SST.
+
+config SPI_FLASH_STMICRO
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by ST MICRO.
+
+config SPI_FLASH_WINBOND
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by Winbond.
+
+config SPI_FLASH_NO_FAST_READ
+ bool
+ default n
+ depends on SPI_FLASH
+ help
+ Select this option if your setup requires to avoid "fast read"s
+ from the SPI flash parts.
diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc
new file mode 100644
index 0000000000..1814e80003
--- /dev/null
+++ b/src/drivers/spi/Makefile.inc
@@ -0,0 +1,12 @@
+# SPI flash driver interface
+ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c
+
+# drivers
+ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c
+ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c
+ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c
+ramstage-$(CONFIG_SPI_FLASH_SST) += sst.c
+ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c
+ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c
+ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
+
diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
new file mode 100644
index 0000000000..4056953098
--- /dev/null
+++ b/src/drivers/spi/eon.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2010, ucRobotics Inc.
+ * Author: Chong Huang <chuang@ucrobotics.com>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* EN25Q128-specific commands */
+#define CMD_EN25Q128_WREN 0x06 /* Write Enable */
+#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */
+#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */
+#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */
+#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */
+#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_EN25Q128_PP 0x02 /* Page Program */
+#define CMD_EN25Q128_SE 0x20 /* Sector Erase */
+#define CMD_EN25Q128_BE 0xd8 /* Block Erase */
+#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
+#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+
+#define EON_ID_EN25Q128 0x18
+
+struct eon_spi_flash_params {
+ u8 idcode1;
+ u16 page_size;
+ u16 pages_per_sector;
+ u16 sectors_per_block;
+ u16 nr_sectors;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct eon_spi_flash {
+ struct spi_flash flash;
+ const struct eon_spi_flash_params *params;
+};
+
+static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct eon_spi_flash, flash);
+}
+
+static const struct eon_spi_flash_params eon_spi_flash_table[] = {
+ {
+ .idcode1 = EON_ID_EN25Q128,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 4096,
+ .name = "EN25Q128",
+ },
+};
+
+static int eon_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = eon->params->page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_EN25Q128_PP;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ printk(BIOS_SPEW,
+ "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: EON Page Program failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ printk(BIOS_INFO, "SF: EON: Successfully programmed %zu bytes @ 0x%x\n",
+ len, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int eon_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len);
+}
+
+struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
+{
+ const struct eon_spi_flash_params *params;
+ struct eon_spi_flash *eon;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
+ params = &eon_spi_flash_table[i];
+ if (params->idcode1 == idcode[2])
+ break;
+ }
+
+ if (i == ARRAY_SIZE(eon_spi_flash_table)) {
+ printk(BIOS_WARNING, "SF: Unsupported EON ID %02x\n", idcode[1]);
+ return NULL;
+ }
+
+ eon = malloc(sizeof(*eon));
+ if (!eon) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ eon->params = params;
+ eon->flash.spi = spi;
+ eon->flash.name = params->name;
+
+ eon->flash.write = eon_write;
+ eon->flash.erase = eon_erase;
+ eon->flash.read = spi_flash_cmd_read_fast;
+ eon->flash.sector_size = params->page_size * params->pages_per_sector
+ * params->sectors_per_block;
+ eon->flash.size = params->page_size * params->pages_per_sector
+ * params->nr_sectors;
+
+ return &eon->flash;
+}
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
new file mode 100644
index 0000000000..130e746827
--- /dev/null
+++ b/src/drivers/spi/macronix.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2009(C) Marvell International Ltd. and its affiliates
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Based on drivers/mtd/spi/stmicro.c
+ *
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan <mcmullan@netapp.com>
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* MX25xx-specific commands */
+#define CMD_MX25XX_WREN 0x06 /* Write Enable */
+#define CMD_MX25XX_WRDI 0x04 /* Write Disable */
+#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */
+#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */
+#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */
+#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_MX25XX_PP 0x02 /* Page Program */
+#define CMD_MX25XX_SE 0x20 /* Sector Erase */
+#define CMD_MX25XX_BE 0xD8 /* Block Erase */
+#define CMD_MX25XX_CE 0xc7 /* Chip Erase */
+#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */
+#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */
+
+#define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */
+
+struct macronix_spi_flash_params {
+ u16 idcode;
+ u16 page_size;
+ u16 pages_per_sector;
+ u16 sectors_per_block;
+ u16 nr_blocks;
+ const char *name;
+};
+
+struct macronix_spi_flash {
+ struct spi_flash flash;
+ const struct macronix_spi_flash_params *params;
+};
+
+static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash
+ *flash)
+{
+ return container_of(flash, struct macronix_spi_flash, flash);
+}
+
+static const struct macronix_spi_flash_params macronix_spi_flash_table[] = {
+ {
+ .idcode = 0x2015,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "MX25L1605D",
+ },
+ {
+ .idcode = 0x2016,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "MX25L3205D",
+ },
+ {
+ .idcode = 0x2017,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "MX25L6405D",
+ },
+ {
+ .idcode = 0x2018,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "MX25L12805D",
+ },
+ {
+ .idcode = 0x2618,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "MX25L12855E",
+ },
+};
+
+static int macronix_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct macronix_spi_flash *mcx = to_macronix_spi_flash(flash);
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = min(mcx->params->page_size, CONTROLLER_PAGE_LIMIT);
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_MX25XX_PP;
+ cmd[1] = (offset >> 16) & 0xff;
+ cmd[2] = (offset >> 8) & 0xff;
+ cmd[3] = offset & 0xff;
+
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Macronix Page Program failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ offset += chunk_len;
+ byte_addr = 0;
+ }
+
+ printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n",
+ len, offset - len);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_MX25XX_SE, offset, len);
+}
+
+struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
+{
+ const struct macronix_spi_flash_params *params;
+ struct macronix_spi_flash *mcx;
+ unsigned int i;
+ u16 id = idcode[2] | idcode[1] << 8;
+
+ for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) {
+ params = &macronix_spi_flash_table[i];
+ if (params->idcode == id)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(macronix_spi_flash_table)) {
+ printk(BIOS_WARNING, "SF: Unsupported Macronix ID %04x\n", id);
+ return NULL;
+ }
+
+ mcx = malloc(sizeof(*mcx));
+ if (!mcx) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ mcx->params = params;
+ mcx->flash.spi = spi;
+ mcx->flash.name = params->name;
+
+ mcx->flash.write = macronix_write;
+ mcx->flash.erase = macronix_erase;
+#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+ mcx->flash.read = spi_flash_cmd_read_slow;
+#else
+ mcx->flash.read = spi_flash_cmd_read_fast;
+#endif
+ mcx->flash.sector_size = params->page_size * params->pages_per_sector;
+ mcx->flash.size = mcx->flash.sector_size * params->sectors_per_block *
+ params->nr_blocks;
+
+ return &mcx->flash;
+}
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
new file mode 100644
index 0000000000..a4f370a6ab
--- /dev/null
+++ b/src/drivers/spi/spansion.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * Author: Mingkai Hu (Mingkai.hu@freescale.com)
+ * Based on stmicro.c by Wolfgang Denk (wd@denx.de),
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com),
+ * and Jason McMullan (mcmullan@netapp.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* S25FLxx-specific commands */
+#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */
+#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */
+#define CMD_S25FLXX_WREN 0x06 /* Write Enable */
+#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */
+#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */
+#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */
+#define CMD_S25FLXX_PP 0x02 /* Page Program */
+#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */
+#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */
+#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */
+#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */
+
+#define SPSN_ID_S25FL008A 0x0213
+#define SPSN_ID_S25FL016A 0x0214
+#define SPSN_ID_S25FL032A 0x0215
+#define SPSN_ID_S25FL064A 0x0216
+#define SPSN_ID_S25FL128P 0x2018
+#define SPSN_EXT_ID_S25FL128P_256KB 0x0300
+#define SPSN_EXT_ID_S25FL128P_64KB 0x0301
+#define SPSN_EXT_ID_S25FL032P 0x4d00
+
+struct spansion_spi_flash_params {
+ u16 idcode1;
+ u16 idcode2;
+ u16 page_size;
+ u16 pages_per_sector;
+ u16 nr_sectors;
+ const char *name;
+};
+
+struct spansion_spi_flash {
+ struct spi_flash flash;
+ const struct spansion_spi_flash_params *params;
+};
+
+static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash
+ *flash)
+{
+ return container_of(flash, struct spansion_spi_flash, flash);
+}
+
+static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
+ {
+ .idcode1 = SPSN_ID_S25FL008A,
+ .idcode2 = 0,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 16,
+ .name = "S25FL008A",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL016A,
+ .idcode2 = 0,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 32,
+ .name = "S25FL016A",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL032A,
+ .idcode2 = 0,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "S25FL032A",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL064A,
+ .idcode2 = 0,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 128,
+ .name = "S25FL064A",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL128P,
+ .idcode2 = SPSN_EXT_ID_S25FL128P_64KB,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 256,
+ .name = "S25FL128P_64K",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL128P,
+ .idcode2 = SPSN_EXT_ID_S25FL128P_256KB,
+ .page_size = 256,
+ .pages_per_sector = 1024,
+ .nr_sectors = 64,
+ .name = "S25FL128P_256K",
+ },
+ {
+ .idcode1 = SPSN_ID_S25FL032A,
+ .idcode2 = SPSN_EXT_ID_S25FL032P,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "S25FL032P",
+ },
+};
+
+static int spansion_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct spansion_spi_flash *spsn = to_spansion_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = spsn->params->page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_S25FLXX_PP;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: SPANSION Page Program failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ printk(BIOS_INFO, "SF: SPANSION: Successfully programmed %zu bytes @ 0x%x\n",
+ len, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len);
+}
+
+struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
+{
+ const struct spansion_spi_flash_params *params;
+ struct spansion_spi_flash *spsn;
+ unsigned int i;
+ unsigned short jedec, ext_jedec;
+
+ jedec = idcode[1] << 8 | idcode[2];
+ ext_jedec = idcode[3] << 8 | idcode[4];
+
+ for (i = 0; i < ARRAY_SIZE(spansion_spi_flash_table); i++) {
+ params = &spansion_spi_flash_table[i];
+ if (params->idcode1 == jedec) {
+ if (params->idcode2 == ext_jedec)
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(spansion_spi_flash_table)) {
+ printk(BIOS_WARNING, "SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec);
+ return NULL;
+ }
+
+ spsn = malloc(sizeof(struct spansion_spi_flash));
+ if (!spsn) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ spsn->params = params;
+ spsn->flash.spi = spi;
+ spsn->flash.name = params->name;
+
+ spsn->flash.write = spansion_write;
+ spsn->flash.erase = spansion_erase;
+ spsn->flash.read = spi_flash_cmd_read_fast;
+ spsn->flash.sector_size = params->page_size * params->pages_per_sector;
+ spsn->flash.size = spsn->flash.sector_size * params->nr_sectors;
+
+ return &spsn->flash;
+}
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
new file mode 100644
index 0000000000..7384cbcf3f
--- /dev/null
+++ b/src/drivers/spi/spi_flash.c
@@ -0,0 +1,309 @@
+/*
+ * SPI flash interface
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <delay.h>
+#include "spi_flash_internal.h"
+
+static void spi_flash_addr(u32 addr, u8 *cmd)
+{
+ /* cmd[0] is actual command */
+ cmd[1] = addr >> 16;
+ cmd[2] = addr >> 8;
+ cmd[3] = addr >> 0;
+}
+
+int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
+{
+ int ret = spi_xfer(spi, &cmd, 8, response, len * 8);
+ if (ret)
+ printk(BIOS_WARNING, "SF: Failed to send command %02x: %d\n", cmd, ret);
+
+ return ret;
+}
+
+int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len)
+{
+ int ret = spi_xfer(spi, cmd, cmd_len * 8, data, data_len * 8);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to send read command (%zu bytes): %d\n",
+ data_len, ret);
+ }
+
+ return ret;
+}
+
+int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
+ const void *data, size_t data_len)
+{
+ int ret;
+ u8 buff[cmd_len + data_len];
+ memcpy(buff, cmd, cmd_len);
+ memcpy(buff + cmd_len, data, data_len);
+
+ ret = spi_xfer(spi, buff, (cmd_len + data_len) * 8, NULL, 0);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to send write command (%zu bytes): %d\n",
+ data_len, ret);
+ }
+
+ return ret;
+}
+
+int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len)
+{
+ struct spi_slave *spi = flash->spi;
+ int ret;
+
+ spi_claim_bus(spi);
+ ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ spi_release_bus(spi);
+
+ return ret;
+}
+
+int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
+ size_t len, void *data)
+{
+ struct spi_slave *spi = flash->spi;
+ u8 cmd[5];
+
+ cmd[0] = CMD_READ_ARRAY_FAST;
+ spi_flash_addr(offset, cmd);
+ cmd[4] = 0x00;
+
+ return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len);
+}
+
+int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset,
+ size_t len, void *data)
+{
+ struct spi_slave *spi = flash->spi;
+ u8 cmd[4];
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ spi_flash_addr(offset, cmd);
+
+ return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len);
+}
+
+int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
+ u8 cmd, u8 poll_bit)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timebase;
+ int ret;
+ u8 status;
+
+ timebase = timeout;
+ do {
+ ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1);
+ if (ret)
+ return -1;
+
+ if ((status & poll_bit) == 0)
+ break;
+
+ mdelay(1);
+ } while (timebase--);
+
+ if ((status & poll_bit) == 0)
+ return 0;
+
+ /* Timed out */
+ printk(BIOS_DEBUG, "SF: time out!\n");
+ return -1;
+}
+
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+ return spi_flash_cmd_poll_bit(flash, timeout,
+ CMD_READ_STATUS, STATUS_WIP);
+}
+
+int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
+ u32 offset, size_t len)
+{
+ u32 start, end, erase_size;
+ int ret;
+ u8 cmd[4];
+
+ erase_size = flash->sector_size;
+ if (offset % erase_size || len % erase_size) {
+ printk(BIOS_WARNING, "SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ cmd[0] = erase_cmd;
+ start = offset;
+ end = start + len;
+
+ while (offset < end) {
+ spi_flash_addr(offset, cmd);
+ offset += erase_size;
+
+ printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], offset);
+
+ ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
+ if (ret)
+ goto out;
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
+ if (ret)
+ goto out;
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+ if (ret)
+ goto out;
+ }
+
+ printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
+
+ out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+/*
+ * The following table holds all device probe functions
+ *
+ * shift: number of continuation bytes before the ID
+ * idcode: the expected IDCODE or 0xff for non JEDEC devices
+ * probe: the function to call
+ *
+ * Non JEDEC devices should be ordered in the table such that
+ * the probe functions with best detection algorithms come first.
+ *
+ * Several matching entries are permitted, they will be tried
+ * in sequence until a probe function returns non NULL.
+ *
+ * IDCODE_CONT_LEN may be redefined if a device needs to declare a
+ * larger "shift" value. IDCODE_PART_LEN generally shouldn't be
+ * changed. This is the max number of bytes probe functions may
+ * examine when looking up part-specific identification info.
+ *
+ * Probe functions will be given the idcode buffer starting at their
+ * manu id byte (the "idcode" in the table below). In other words,
+ * all of the continuation bytes will be skipped (the "shift" below).
+ */
+#define IDCODE_CONT_LEN 0
+#define IDCODE_PART_LEN 5
+static const struct {
+ const u8 shift;
+ const u8 idcode;
+ struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
+} flashes[] = {
+ /* Keep it sorted by define name */
+#if CONFIG_SPI_FLASH_EON
+ { 0, 0x1c, spi_flash_probe_eon, },
+#endif
+#if CONFIG_SPI_FLASH_MACRONIX
+ { 0, 0xc2, spi_flash_probe_macronix, },
+#endif
+#if CONFIG_SPI_FLASH_SPANSION
+ { 0, 0x01, spi_flash_probe_spansion, },
+#endif
+#if CONFIG_SPI_FLASH_SST
+ { 0, 0xbf, spi_flash_probe_sst, },
+#endif
+#if CONFIG_SPI_FLASH_STMICRO
+ { 0, 0x20, spi_flash_probe_stmicro, },
+#endif
+#if CONFIG_SPI_FLASH_WINBOND
+ { 0, 0xef, spi_flash_probe_winbond, },
+#endif
+ /* Keep it sorted by best detection */
+#if CONFIG_SPI_FLASH_STMICRO
+ { 0, 0xff, spi_flash_probe_stmicro, },
+#endif
+};
+#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ struct spi_flash *flash = NULL;
+ int ret, i, shift;
+ u8 idcode[IDCODE_LEN], *idp;
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printk(BIOS_WARNING, "SF: Failed to set up slave\n");
+ return NULL;
+ }
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ /* Read the ID codes */
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+ if (ret)
+ goto err_read_id;
+
+#if CONFIG_DEBUG_SPI_FLASH
+ printk(BIOS_SPEW, "SF: Got idcodes\n");
+ print_buffer(0, idcode, 1, sizeof(idcode), 0);
+#endif
+
+ /* count the number of continuation bytes */
+ for (shift = 0, idp = idcode;
+ shift < IDCODE_CONT_LEN && *idp == 0x7f;
+ ++shift, ++idp)
+ continue;
+
+ /* search the table for matches in shift and id */
+ for (i = 0; i < ARRAY_SIZE(flashes); ++i)
+ if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
+ /* we have a match, call probe */
+ flash = flashes[i].probe(spi, idp);
+ if (flash)
+ break;
+ }
+
+ if (!flash) {
+ printk(BIOS_WARNING, "SF: Unsupported manufacturer %02x\n", *idp);
+ goto err_manufacturer_probe;
+ }
+
+ printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
+ flash->name, flash->sector_size, flash->size);
+
+ spi_release_bus(spi);
+
+ return flash;
+
+err_manufacturer_probe:
+err_read_id:
+ spi_release_bus(spi);
+err_claim_bus:
+ spi_free_slave(spi);
+ return NULL;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ spi_free_slave(flash->spi);
+ free(flash);
+}
diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h
new file mode 100644
index 0000000000..b895e2b4f3
--- /dev/null
+++ b/src/drivers/spi/spi_flash_internal.h
@@ -0,0 +1,81 @@
+/*
+ * SPI flash internal definitions
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ */
+
+/* Common parameters -- kind of high, but they should only occur when there
+ * is a problem (and well your system already is broken), so err on the side
+ * of caution in case we're dealing with slower SPI buses and/or processors.
+ */
+#define CONFIG_SYS_HZ 100
+#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
+
+/* Common commands */
+#define CMD_READ_ID 0x9f
+
+#define CMD_READ_ARRAY_SLOW 0x03
+#define CMD_READ_ARRAY_FAST 0x0b
+#define CMD_READ_ARRAY_LEGACY 0xe8
+
+#define CMD_READ_STATUS 0x05
+#define CMD_WRITE_ENABLE 0x06
+
+/* Common status */
+#define STATUS_WIP 0x01
+
+/* Send a single-byte command to the device and read the response */
+int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
+
+/*
+ * Send a multi-byte command to the device and read the response. Used
+ * for flash array reads, etc.
+ */
+int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len);
+
+int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
+ size_t len, void *data);
+
+int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset,
+ size_t len, void *data);
+
+/*
+ * Send a multi-byte command to the device followed by (optional)
+ * data. Used for programming the flash array, etc.
+ */
+int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
+ const void *data, size_t data_len);
+
+/*
+ * Same as spi_flash_cmd_read() except it also claims/releases the SPI
+ * bus. Used as common part of the ->read() operation.
+ */
+int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len);
+
+/* Send a command to the device and wait for some bit to clear itself. */
+int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
+ u8 cmd, u8 poll_bit);
+
+/*
+ * Send the read status command to the device and wait for the wip
+ * (write-in-progress) bit to clear itself.
+ */
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
+
+/* Erase sectors. */
+int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
+ u32 offset, size_t len);
+
+/* Manufacturer-specific probe functions */
+struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c
new file mode 100644
index 0000000000..56cc851acf
--- /dev/null
+++ b/src/drivers/spi/sst.c
@@ -0,0 +1,268 @@
+/*
+ * Driver for SST serial flashes
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan <mcmullan@netapp.com>
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+#define CMD_SST_WREN 0x06 /* Write Enable */
+#define CMD_SST_WRDI 0x04 /* Write Disable */
+#define CMD_SST_RDSR 0x05 /* Read Status Register */
+#define CMD_SST_WRSR 0x01 /* Write Status Register */
+#define CMD_SST_READ 0x03 /* Read Data Bytes */
+#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_SST_BP 0x02 /* Byte Program */
+#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */
+#define CMD_SST_SE 0x20 /* Sector Erase */
+
+#define SST_SR_WIP (1 << 0) /* Write-in-Progress */
+#define SST_SR_WEL (1 << 1) /* Write enable */
+#define SST_SR_BP0 (1 << 2) /* Block Protection 0 */
+#define SST_SR_BP1 (1 << 3) /* Block Protection 1 */
+#define SST_SR_BP2 (1 << 4) /* Block Protection 2 */
+#define SST_SR_AAI (1 << 6) /* Addressing mode */
+#define SST_SR_BPL (1 << 7) /* BP bits lock */
+
+struct sst_spi_flash_params {
+ u8 idcode1;
+ u16 nr_sectors;
+ const char *name;
+};
+
+struct sst_spi_flash {
+ struct spi_flash flash;
+ const struct sst_spi_flash_params *params;
+};
+
+static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct sst_spi_flash, flash);
+}
+
+#define SST_SECTOR_SIZE (4 * 1024)
+static const struct sst_spi_flash_params sst_spi_flash_table[] = {
+ {
+ .idcode1 = 0x8d,
+ .nr_sectors = 128,
+ .name = "SST25VF040B",
+ },{
+ .idcode1 = 0x8e,
+ .nr_sectors = 256,
+ .name = "SST25VF080B",
+ },{
+ .idcode1 = 0x41,
+ .nr_sectors = 512,
+ .name = "SST25VF016B",
+ },{
+ .idcode1 = 0x4a,
+ .nr_sectors = 1024,
+ .name = "SST25VF032B",
+ },{
+ .idcode1 = 0x4b,
+ .nr_sectors = 2048,
+ .name = "SST25VF064C",
+ },{
+ .idcode1 = 0x01,
+ .nr_sectors = 16,
+ .name = "SST25WF512",
+ },{
+ .idcode1 = 0x02,
+ .nr_sectors = 32,
+ .name = "SST25WF010",
+ },{
+ .idcode1 = 0x03,
+ .nr_sectors = 64,
+ .name = "SST25WF020",
+ },{
+ .idcode1 = 0x04,
+ .nr_sectors = 128,
+ .name = "SST25WF040",
+ },
+};
+
+static int
+sst_enable_writing(struct spi_flash *flash)
+{
+ int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0);
+ if (ret)
+ printk(BIOS_WARNING, "SF: Enabling Write failed\n");
+ return ret;
+}
+
+static int
+sst_disable_writing(struct spi_flash *flash)
+{
+ int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0);
+ if (ret)
+ printk(BIOS_WARNING, "SF: Disabling Write failed\n");
+ return ret;
+}
+
+static int
+sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
+{
+ int ret;
+ u8 cmd[4] = {
+ CMD_SST_BP,
+ offset >> 16,
+ offset >> 8,
+ offset,
+ };
+
+ printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
+ spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset);
+
+ ret = sst_enable_writing(flash);
+ if (ret)
+ return ret;
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ if (ret)
+ return ret;
+
+ return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+}
+
+static int
+sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
+{
+ size_t actual, cmd_len;
+ int ret;
+ u8 cmd[4];
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ /* If the data is not word aligned, write out leading single byte */
+ actual = offset % 2;
+ if (actual) {
+ ret = sst_byte_write(flash, offset, buf);
+ if (ret)
+ goto done;
+ }
+ offset += actual;
+
+ ret = sst_enable_writing(flash);
+ if (ret)
+ goto done;
+
+ cmd_len = 4;
+ cmd[0] = CMD_SST_AAI_WP;
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset;
+
+ for (; actual < len - 1; actual += 2) {
+ printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
+ spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0],
+ offset);
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ buf + actual, 2);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: SST word program failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ cmd_len = 1;
+ offset += 2;
+ }
+
+ if (!ret)
+ ret = sst_disable_writing(flash);
+
+ /* If there is a single trailing byte, write it out */
+ if (!ret && actual != len)
+ ret = sst_byte_write(flash, offset, buf + actual);
+
+ done:
+ printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n",
+ ret ? "failure" : "success", len, offset - actual);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int sst_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_SST_SE, offset, len);
+}
+
+static int
+sst_unlock(struct spi_flash *flash)
+{
+ int ret;
+ u8 cmd, status;
+
+ ret = sst_enable_writing(flash);
+ if (ret)
+ return ret;
+
+ cmd = CMD_SST_WRSR;
+ status = 0;
+ ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1);
+ if (ret)
+ printk(BIOS_WARNING, "SF: Unable to set status byte\n");
+
+ printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR));
+
+ return ret;
+}
+
+struct spi_flash *
+spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode)
+{
+ const struct sst_spi_flash_params *params;
+ struct sst_spi_flash *stm;
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) {
+ params = &sst_spi_flash_table[i];
+ if (params->idcode1 == idcode[2])
+ break;
+ }
+
+ if (i == ARRAY_SIZE(sst_spi_flash_table)) {
+ printk(BIOS_WARNING, "SF: Unsupported SST ID %02x\n", idcode[1]);
+ return NULL;
+ }
+
+ stm = malloc(sizeof(*stm));
+ if (!stm) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ stm->params = params;
+ stm->flash.spi = spi;
+ stm->flash.name = params->name;
+
+ stm->flash.write = sst_write;
+ stm->flash.erase = sst_erase;
+ stm->flash.read = spi_flash_cmd_read_fast;
+ stm->flash.sector_size = SST_SECTOR_SIZE;
+ stm->flash.size = stm->flash.sector_size * params->nr_sectors;
+
+ /* Flash powers up read-only, so clear BP# bits */
+ sst_unlock(&stm->flash);
+
+ return &stm->flash;
+}
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
new file mode 100644
index 0000000000..8cbdad5e48
--- /dev/null
+++ b/src/drivers/spi/stmicro.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan <mcmullan@netapp.com>
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* M25Pxx-specific commands */
+#define CMD_M25PXX_WREN 0x06 /* Write Enable */
+#define CMD_M25PXX_WRDI 0x04 /* Write Disable */
+#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */
+#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */
+#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */
+#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_M25PXX_PP 0x02 /* Page Program */
+#define CMD_M25PXX_SE 0xd8 /* Sector Erase */
+#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */
+#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */
+#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */
+
+#define STM_ID_M25P10 0x11
+#define STM_ID_M25P16 0x15
+#define STM_ID_M25P20 0x12
+#define STM_ID_M25P32 0x16
+#define STM_ID_M25P40 0x13
+#define STM_ID_M25P64 0x17
+#define STM_ID_M25P80 0x14
+#define STM_ID_M25P128 0x18
+
+struct stmicro_spi_flash_params {
+ u8 idcode1;
+ u16 page_size;
+ u16 pages_per_sector;
+ u16 nr_sectors;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct stmicro_spi_flash {
+ struct spi_flash flash;
+ const struct stmicro_spi_flash_params *params;
+};
+
+static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash
+ *flash)
+{
+ return container_of(flash, struct stmicro_spi_flash, flash);
+}
+
+static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = {
+ {
+ .idcode1 = STM_ID_M25P10,
+ .page_size = 256,
+ .pages_per_sector = 128,
+ .nr_sectors = 4,
+ .name = "M25P10",
+ },
+ {
+ .idcode1 = STM_ID_M25P16,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 32,
+ .name = "M25P16",
+ },
+ {
+ .idcode1 = STM_ID_M25P20,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 4,
+ .name = "M25P20",
+ },
+ {
+ .idcode1 = STM_ID_M25P32,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "M25P32",
+ },
+ {
+ .idcode1 = STM_ID_M25P40,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 8,
+ .name = "M25P40",
+ },
+ {
+ .idcode1 = STM_ID_M25P64,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 128,
+ .name = "M25P64",
+ },
+ {
+ .idcode1 = STM_ID_M25P80,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 16,
+ .name = "M25P80",
+ },
+ {
+ .idcode1 = STM_ID_M25P128,
+ .page_size = 256,
+ .pages_per_sector = 1024,
+ .nr_sectors = 64,
+ .name = "M25P128",
+ },
+};
+
+static int stmicro_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = stm->params->page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_M25PXX_PP;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: STMicro Page Program failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ break;
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ printk(BIOS_INFO, "SF: STMicro: Successfully programmed %zu bytes @ 0x%x\n",
+ len, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_M25PXX_SE, offset, len);
+}
+
+struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
+{
+ const struct stmicro_spi_flash_params *params;
+ struct stmicro_spi_flash *stm;
+ unsigned int i;
+
+ if (idcode[0] == 0xff) {
+ i = spi_flash_cmd(spi, CMD_M25PXX_RES,
+ idcode, 4);
+ if (i)
+ return NULL;
+ if ((idcode[3] & 0xf0) == 0x10) {
+ idcode[0] = 0x20;
+ idcode[1] = 0x20;
+ idcode[2] = idcode[3] + 1;
+ } else
+ return NULL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) {
+ params = &stmicro_spi_flash_table[i];
+ if (params->idcode1 == idcode[2]) {
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
+ printk(BIOS_WARNING, "SF: Unsupported STMicro ID %02x\n", idcode[1]);
+ return NULL;
+ }
+
+ stm = malloc(sizeof(struct stmicro_spi_flash));
+ if (!stm) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ stm->params = params;
+ stm->flash.spi = spi;
+ stm->flash.name = params->name;
+
+ stm->flash.write = stmicro_write;
+ stm->flash.erase = stmicro_erase;
+ stm->flash.read = spi_flash_cmd_read_fast;
+ stm->flash.sector_size = params->page_size * params->pages_per_sector;
+ stm->flash.size = stm->flash.sector_size * params->nr_sectors;
+
+ return &stm->flash;
+}
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
new file mode 100644
index 0000000000..65818d56f3
--- /dev/null
+++ b/src/drivers/spi/winbond.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2008, Network Appliance Inc.
+ * Author: Jason McMullan <mcmullan <at> netapp.com>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* M25Pxx-specific commands */
+#define CMD_W25_WREN 0x06 /* Write Enable */
+#define CMD_W25_WRDI 0x04 /* Write Disable */
+#define CMD_W25_RDSR 0x05 /* Read Status Register */
+#define CMD_W25_WRSR 0x01 /* Write Status Register */
+#define CMD_W25_READ 0x03 /* Read Data Bytes */
+#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_W25_PP 0x02 /* Page Program */
+#define CMD_W25_SE 0x20 /* Sector (4K) Erase */
+#define CMD_W25_BE 0xd8 /* Block (64K) Erase */
+#define CMD_W25_CE 0xc7 /* Chip Erase */
+#define CMD_W25_DP 0xb9 /* Deep Power-down */
+#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
+
+struct winbond_spi_flash_params {
+ uint16_t id;
+ /* Log2 of page size in power-of-two mode */
+ uint8_t l2_page_size;
+ uint16_t pages_per_sector;
+ uint16_t sectors_per_block;
+ uint16_t nr_blocks;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct winbond_spi_flash {
+ struct spi_flash flash;
+ const struct winbond_spi_flash_params *params;
+};
+
+static inline struct winbond_spi_flash *
+to_winbond_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct winbond_spi_flash, flash);
+}
+
+static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
+ {
+ .id = 0x3015,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "W25X16",
+ },
+ {
+ .id = 0x3016,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "W25X32",
+ },
+ {
+ .id = 0x3017,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "W25X64",
+ },
+ {
+ .id = 0x4015,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "W25Q16",
+ },
+ {
+ .id = 0x4016,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "W25Q32",
+ },
+ {
+ .id = 0x4017,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "W25Q64",
+ },
+ {
+ .id = 0x4018,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "W25Q128",
+ },
+};
+
+static int winbond_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT);
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_W25_PP;
+ cmd[1] = (offset >> 16) & 0xff;
+ cmd[2] = (offset >> 8) & 0xff;
+ cmd[3] = offset & 0xff;
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n",
+ buf + actual,
+ cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Enabling Write failed\n");
+ goto out;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ printk(BIOS_WARNING, "SF: Winbond Page Program failed\n");
+ goto out;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ goto out;
+
+ offset += chunk_len;
+ byte_addr = 0;
+ }
+
+ printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n",
+ len, offset - len);
+ ret = 0;
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
+}
+
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
+{
+ const struct winbond_spi_flash_params *params;
+ unsigned page_size;
+ struct winbond_spi_flash *stm;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
+ params = &winbond_spi_flash_table[i];
+ if (params->id == ((idcode[1] << 8) | idcode[2]))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
+ printk(BIOS_WARNING, "SF: Unsupported Winbond ID %02x%02x\n",
+ idcode[1], idcode[2]);
+ return NULL;
+ }
+
+ stm = malloc(sizeof(struct winbond_spi_flash));
+ if (!stm) {
+ printk(BIOS_WARNING, "SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ stm->params = params;
+ stm->flash.spi = spi;
+ stm->flash.name = params->name;
+
+ /* Assuming power-of-two page size initially. */
+ page_size = 1 << params->l2_page_size;
+
+ stm->flash.write = winbond_write;
+ stm->flash.erase = winbond_erase;
+#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+ stm->flash.read = spi_flash_cmd_read_slow;
+#else
+ stm->flash.read = spi_flash_cmd_read_fast;
+#endif
+ stm->flash.sector_size = (1 << stm->params->l2_page_size) *
+ stm->params->pages_per_sector;
+ stm->flash.size = page_size * params->pages_per_sector
+ * params->sectors_per_block
+ * params->nr_blocks;
+
+ return &stm->flash;
+}
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a2d68844e0..176529344e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2502,6 +2502,10 @@
#define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914
#define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
+#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
+
/* Intel 82801E (C-ICH) */
#define PCI_DEVICE_ID_INTEL_82801E_LPC 0x2450
#define PCI_DEVICE_ID_INTEL_82801E_USB 0x2452
diff --git a/src/include/spi.h b/src/include/spi.h
new file mode 100644
index 0000000000..bb84258137
--- /dev/null
+++ b/src/include/spi.h
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPI_H_
+#define _SPI_H_
+
+#include <stdint.h>
+
+/* Controller-specific definitions: */
+
+/* SPI mode flags */
+#define SPI_CPHA 0x01 /* clock phase */
+#define SPI_CPOL 0x02 /* clock polarity */
+#define SPI_MODE_0 (0|0) /* (original MicroWire) */
+#define SPI_MODE_1 (0|SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL|0)
+#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
+#define SPI_CS_HIGH 0x04 /* CS active high */
+#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
+#define SPI_3WIRE 0x10 /* SI/SO signals shared */
+#define SPI_LOOP 0x20 /* loopback mode */
+
+/* SPI transfer flags */
+#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
+#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
+
+/*-----------------------------------------------------------------------
+ * Representation of a SPI slave, i.e. what we're communicating with.
+ *
+ * Drivers are expected to extend this with controller-specific data.
+ *
+ * bus: ID of the bus that the slave is attached to.
+ * cs: ID of the chip select connected to the slave.
+ */
+struct spi_slave {
+ unsigned int bus;
+ unsigned int cs;
+};
+
+/*-----------------------------------------------------------------------
+ * Initialization, must be called once on start up.
+ *
+ * TODO: I don't think we really need this.
+ */
+void spi_init(void);
+
+/*-----------------------------------------------------------------------
+ * Set up communications parameters for a SPI slave.
+ *
+ * This must be called once for each slave. Note that this function
+ * usually doesn't touch any actual hardware, it only initializes the
+ * contents of spi_slave so that the hardware can be easily
+ * initialized later.
+ *
+ * bus: Bus ID of the slave chip.
+ * cs: Chip select ID of the slave chip on the specified bus.
+ * max_hz: Maximum SCK rate in Hz.
+ * mode: Clock polarity, clock phase and other parameters.
+ *
+ * Returns: A spi_slave reference that can be used in subsequent SPI
+ * calls, or NULL if one or more of the parameters are not supported.
+ */
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode);
+
+/*-----------------------------------------------------------------------
+ * Free any memory associated with a SPI slave.
+ *
+ * slave: The SPI slave
+ */
+void spi_free_slave(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * slave: The SPI slave
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int spi_claim_bus(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Release the SPI bus
+ *
+ * This must be called once for every call to spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * slave: The SPI slave
+ */
+void spi_release_bus(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port. That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter. Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * spi_xfer() interface:
+ * slave: The SPI slave which will be sending/receiving the data.
+ * dout: Pointer to a string of bits to send out. The bits are
+ * held in a byte array and are sent MSB first.
+ * bitsout: How many bits to write.
+ * din: Pointer to a string of bits that will be filled in.
+ * bitsin: How many bits to read.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
+ void *din, unsigned int bitsin);
+
+/*-----------------------------------------------------------------------
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs);
+
+/*-----------------------------------------------------------------------
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Set transfer speed.
+ * This sets a new speed to be applied for next spi_xfer().
+ * slave: The SPI slave
+ * hz: The transfer speed
+ */
+void spi_set_speed(struct spi_slave *slave, uint32_t hz);
+
+/*-----------------------------------------------------------------------
+ * Write 8 bits, then read 8 bits.
+ * slave: The SPI slave we're communicating with
+ * byte: Byte to be written
+ *
+ * Returns: The value that was read, or a negative value on error.
+ *
+ * TODO: This function probably shouldn't be inlined.
+ */
+static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
+{
+ unsigned char dout[2];
+ unsigned char din[2];
+ int ret;
+
+ dout[0] = byte;
+ dout[1] = 0;
+
+ ret = spi_xfer(slave, dout, 16, din, 16);
+ return ret < 0 ? ret : din[1];
+}
+
+#endif /* _SPI_H_ */
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
new file mode 100644
index 0000000000..2a1dcd4632
--- /dev/null
+++ b/src/include/spi_flash.h
@@ -0,0 +1,91 @@
+/*
+ * Interface to SPI flash
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SPI_FLASH_H_
+#define _SPI_FLASH_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <console/console.h>
+#include <spi.h>
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#define min(a, b) ((a)<(b)?(a):(b))
+
+#define CONFIG_ICH_SPI
+#ifdef CONFIG_ICH_SPI
+#define CONTROLLER_PAGE_LIMIT 64
+#else
+/* any number larger than 4K would do, actually */
+#define CONTROLLER_PAGE_LIMIT ((int)(~0U>>1))
+#endif
+
+struct spi_flash {
+ struct spi_slave *spi;
+
+ const char *name;
+
+ u32 size;
+
+ u32 sector_size;
+
+ int (*read)(struct spi_flash *flash, u32 offset,
+ size_t len, void *buf);
+ int (*write)(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf);
+ int (*erase)(struct spi_flash *flash, u32 offset,
+ size_t len);
+};
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+void spi_flash_free(struct spi_flash *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+ size_t len, void *buf)
+{
+ return flash->read(flash, offset, len, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ return flash->write(flash, offset, len, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+ size_t len)
+{
+ return flash->erase(flash, offset, len);
+}
+
+#endif /* _SPI_FLASH_H_ */
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 3891be13b0..33dfe9d755 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
+ select SPI_FLASH
+ select SPI_FLASH_NO_FAST_READ
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 57322542ac..f086426aa5 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -34,6 +34,8 @@ ramstage-y += me_status.c
ramstage-y += reset.c
ramstage-y += watchdog.c
+ramstage-y += spi.c
+
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
new file mode 100644
index 0000000000..2508a969fb
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is derived from the flashrom project. */
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include <spi.h>
+
+#define min(a, b) ((a)<(b)?(a):(b))
+
+typedef device_t pci_dev_t;
+#define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg)
+#define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg)
+#define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg)
+#define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val)
+
+typedef struct spi_slave ich_spi_slave;
+
+static int ichspi_lock = 0;
+
+typedef struct ich7_spi_regs {
+ uint16_t spis;
+ uint16_t spic;
+ uint32_t spia;
+ uint64_t spid[8];
+ uint64_t _pad;
+ uint32_t bbar;
+ uint16_t preop;
+ uint16_t optype;
+ uint8_t opmenu[8];
+} __attribute__((packed)) ich7_spi_regs;
+
+typedef struct ich9_spi_regs {
+ uint32_t bfpr;
+ uint16_t hsfs;
+ uint16_t hsfc;
+ uint32_t faddr;
+ uint32_t _reserved0;
+ uint32_t fdata[16];
+ uint32_t frap;
+ uint32_t freg[5];
+ uint32_t _reserved1[3];
+ uint32_t pr[5];
+ uint32_t _reserved2[2];
+ uint8_t ssfs;
+ uint8_t ssfc[3];
+ uint16_t preop;
+ uint16_t optype;
+ uint8_t opmenu[8];
+ uint32_t bbar;
+ uint8_t _reserved3[12];
+ uint32_t fdoc;
+ uint32_t fdod;
+ uint8_t _reserved4[8];
+ uint32_t afc;
+ uint32_t lvscc;
+ uint32_t uvscc;
+ uint8_t _reserved5[4];
+ uint32_t fpb;
+ uint8_t _reserved6[28];
+ uint32_t srdl;
+ uint32_t srdc;
+ uint32_t srd;
+} __attribute__((packed)) ich9_spi_regs;
+
+typedef struct ich_spi_controller {
+ int locked;
+
+ uint8_t *opmenu;
+ int menubytes;
+ uint16_t *preop;
+ uint16_t *optype;
+ uint32_t *addr;
+ uint8_t *data;
+ unsigned databytes;
+ uint8_t *status;
+ uint16_t *control;
+ uint32_t *bbar;
+} ich_spi_controller;
+
+static ich_spi_controller cntlr;
+
+enum {
+ SPIS_SCIP = 0x0001,
+ SPIS_GRANT = 0x0002,
+ SPIS_CDS = 0x0004,
+ SPIS_FCERR = 0x0008,
+ SSFS_AEL = 0x0010,
+ SPIS_LOCK = 0x8000,
+ SPIS_RESERVED_MASK = 0x7ff0,
+ SSFS_RESERVED_MASK = 0x7fe2
+};
+
+enum {
+ SPIC_SCGO = 0x000002,
+ SPIC_ACS = 0x000004,
+ SPIC_SPOP = 0x000008,
+ SPIC_DBC = 0x003f00,
+ SPIC_DS = 0x004000,
+ SPIC_SME = 0x008000,
+ SSFC_SCF_MASK = 0x070000,
+ SSFC_RESERVED = 0xf80000
+};
+
+enum {
+ HSFS_FDONE = 0x0001,
+ HSFS_FCERR = 0x0002,
+ HSFS_AEL = 0x0004,
+ HSFS_BERASE_MASK = 0x0018,
+ HSFS_BERASE_SHIFT = 3,
+ HSFS_SCIP = 0x0020,
+ HSFS_FDOPSS = 0x2000,
+ HSFS_FDV = 0x4000,
+ HSFS_FLOCKDN = 0x8000
+};
+
+enum {
+ HSFC_FGO = 0x0001,
+ HSFC_FCYCLE_MASK = 0x0006,
+ HSFC_FCYCLE_SHIFT = 1,
+ HSFC_FDBC_MASK = 0x3f00,
+ HSFC_FDBC_SHIFT = 8,
+ HSFC_FSMIE = 0x8000
+};
+
+enum {
+ SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
+ SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
+ SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
+ SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
+};
+
+#if CONFIG_DEBUG_SPI_FLASH
+
+static u8 readb_(const void *addr)
+{
+ u8 v = readb(addr);
+ printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
+ v, ((unsigned) addr & 0xffff) - 0xf020);
+ return v;
+}
+
+static u16 readw_(const void *addr)
+{
+ u16 v = readw(addr);
+ printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
+ v, ((unsigned) addr & 0xffff) - 0xf020);
+ return v;
+}
+
+static u32 readl_(const void *addr)
+{
+ u32 v = readl(addr);
+ printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
+ v, ((unsigned) addr & 0xffff) - 0xf020);
+ return v;
+}
+
+static void writeb_(u8 b, const void *addr)
+{
+ writeb(b, addr);
+ printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
+ b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+static void writew_(u16 b, const void *addr)
+{
+ writew(b, addr);
+ printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
+ b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+static void writel_(u32 b, const void *addr)
+{
+ writel(b, addr);
+ printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
+ b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
+
+#define readb_(a) read8((uint32_t)a)
+#define readw_(a) read16((uint32_t)a)
+#define readl_(a) read32((uint32_t)a)
+#define writeb_(val, addr) write8((uint32_t)addr, val)
+#define writew_(val, addr) write16((uint32_t)addr, val)
+#define writel_(val, addr) write32((uint32_t)addr, val)
+
+#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
+
+static void write_reg(const void *value, void *dest, uint32_t size)
+{
+ const uint8_t *bvalue = value;
+ uint8_t *bdest = dest;
+
+ while (size >= 4) {
+ writel_(*(const uint32_t *)bvalue, bdest);
+ bdest += 4; bvalue += 4; size -= 4;
+ }
+ while (size) {
+ writeb_(*bvalue, bdest);
+ bdest++; bvalue++; size--;
+ }
+}
+
+static void read_reg(const void *src, void *value, uint32_t size)
+{
+ const uint8_t *bsrc = src;
+ uint8_t *bvalue = value;
+
+ while (size >= 4) {
+ *(uint32_t *)bvalue = readl_(bsrc);
+ bsrc += 4; bvalue += 4; size -= 4;
+ }
+ while (size) {
+ *bvalue = readb_(bsrc);
+ bsrc++; bvalue++; size--;
+ }
+}
+
+static void ich_set_bbar(uint32_t minaddr)
+{
+ const uint32_t bbar_mask = 0x00ffff00;
+ uint32_t ichspi_bbar;
+
+ minaddr &= bbar_mask;
+ ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
+ ichspi_bbar |= minaddr;
+ writel_(ichspi_bbar, cntlr.bbar);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n");
+ return 0;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ ich_spi_slave *slave = malloc(sizeof(*slave));
+
+ if (!slave) {
+ printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n");
+ return NULL;
+ }
+
+ memset(slave, 0, sizeof(*slave));
+
+ slave->bus = bus;
+ slave->cs = cs;
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *_slave)
+{
+ ich_spi_slave *slave = (ich_spi_slave *)_slave;
+ free(slave);
+}
+
+static inline int spi_is_cougarpoint_lpc(uint16_t device_id)
+{
+ return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
+ device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX;
+};
+
+void spi_init(void)
+{
+ int ich_version = 0;
+
+ uint8_t *rcrb; /* Root Complex Register Block */
+ uint32_t rcba; /* Root Complex Base Address */
+ uint8_t bios_cntl;
+ pci_dev_t dev;
+ uint32_t ids;
+ uint16_t vendor_id, device_id;
+
+ dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+ pci_read_config_dword(dev, 0, &ids);
+ vendor_id = ids;
+ device_id = (ids >> 16);
+
+ if (vendor_id != PCI_VENDOR_ID_INTEL) {
+ printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n");
+ return;
+ }
+
+ if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) {
+ ich_version = 7;
+ } else if (spi_is_cougarpoint_lpc(device_id)) {
+ ich_version = 9;
+ } else {
+ printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n");
+ return;
+ }
+
+ pci_read_config_dword(dev, 0xf0, &rcba);
+ /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
+ rcrb = (uint8_t *)(rcba & 0xffffc000);
+ switch (ich_version) {
+ case 7:
+ {
+ const uint16_t ich7_spibar_offset = 0x3020;
+ ich7_spi_regs *ich7_spi =
+ (ich7_spi_regs *)(rcrb + ich7_spibar_offset);
+
+ ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK;
+ cntlr.opmenu = ich7_spi->opmenu;
+ cntlr.menubytes = sizeof(ich7_spi->opmenu);
+ cntlr.optype = &ich7_spi->optype;
+ cntlr.addr = &ich7_spi->spia;
+ cntlr.data = (uint8_t *)ich7_spi->spid;
+ cntlr.databytes = sizeof(ich7_spi->spid);
+ cntlr.status = (uint8_t *)&ich7_spi->spis;
+ cntlr.control = &ich7_spi->spic;
+ cntlr.bbar = &ich7_spi->bbar;
+ cntlr.preop = &ich7_spi->preop;
+ break;
+ }
+ case 9:
+ {
+ const uint16_t ich9_spibar_offset = 0x3800;
+ ich9_spi_regs *ich9_spi =
+ (ich9_spi_regs *)(rcrb + ich9_spibar_offset);
+ ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ cntlr.opmenu = ich9_spi->opmenu;
+ cntlr.menubytes = sizeof(ich9_spi->opmenu);
+ cntlr.optype = &ich9_spi->optype;
+ cntlr.addr = &ich9_spi->faddr;
+ cntlr.data = (uint8_t *)ich9_spi->fdata;
+ cntlr.databytes = sizeof(ich9_spi->fdata);
+ cntlr.status = &ich9_spi->ssfs;
+ cntlr.control = (uint16_t *)ich9_spi->ssfc;
+ cntlr.bbar = &ich9_spi->bbar;
+ cntlr.preop = &ich9_spi->preop;
+ break;
+ }
+ default:
+ printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version);
+ }
+
+ ich_set_bbar(0);
+
+ /* Disable the BIOS write protect so write commands are allowed. */
+ pci_read_config_byte(dev, 0xdc, &bios_cntl);
+ switch (ich_version) {
+ case 9:
+ /* Deassert SMM BIOS Write Protect Disable. */
+ bios_cntl &= ~(1 << 5);
+ break;
+
+ default:
+ break;
+ }
+ pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+}
+
+typedef struct spi_transaction {
+ const uint8_t *out;
+ uint32_t bytesout;
+ uint8_t *in;
+ uint32_t bytesin;
+ uint8_t type;
+ uint8_t opcode;
+ uint32_t offset;
+} spi_transaction;
+
+static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+{
+ trans->out += bytes;
+ trans->bytesout -= bytes;
+}
+
+static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+{
+ trans->in += bytes;
+ trans->bytesin -= bytes;
+}
+
+static void spi_setup_type(spi_transaction *trans)
+{
+ trans->type = 0xFF;
+
+ /* Try to guess spi type from read/write sizes. */
+ if (trans->bytesin == 0) {
+ if (trans->bytesout > 4)
+ /*
+ * If bytesin = 0 and bytesout > 4, we presume this is
+ * a write data operation, which is accompanied by an
+ * address.
+ */
+ trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
+ else
+ trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
+ return;
+ }
+
+ if (trans->bytesout == 1) { /* and bytesin is > 0 */
+ trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
+ return;
+ }
+
+ if (trans->bytesout == 4) { /* and bytesin is > 0 */
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ }
+}
+
+static int spi_setup_opcode(spi_transaction *trans)
+{
+ uint16_t optypes;
+ uint8_t opmenu[cntlr.menubytes];
+
+ trans->opcode = trans->out[0];
+ spi_use_out(trans, 1);
+ if (!ichspi_lock) {
+ /* The lock is off, so just use index 0. */
+ writeb_(trans->opcode, cntlr.opmenu);
+ optypes = readw_(cntlr.optype);
+ optypes = (optypes & 0xfffc) | (trans->type & 0x3);
+ writew_(optypes, cntlr.optype);
+ return 0;
+ } else {
+ /* The lock is on. See if what we need is on the menu. */
+ uint8_t optype;
+ uint16_t opcode_index;
+
+ read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
+ for (opcode_index = 0; opcode_index < cntlr.menubytes;
+ opcode_index++) {
+ if (opmenu[opcode_index] == trans->opcode)
+ break;
+ }
+
+ if (opcode_index == cntlr.menubytes) {
+ printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
+ trans->opcode);
+ return -1;
+ }
+
+ optypes = readw_(cntlr.optype);
+ optype = (optypes >> (opcode_index * 2)) & 0x3;
+ if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
+ optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
+ trans->bytesout >= 3) {
+ /* We guessed wrong earlier. Fix it up. */
+ trans->type = optype;
+ }
+ if (optype != trans->type) {
+ printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
+ optype);
+ return -1;
+ }
+ return opcode_index;
+ }
+}
+
+static int spi_setup_offset(spi_transaction *trans)
+{
+ /* Separate the SPI address and data. */
+ switch (trans->type) {
+ case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
+ case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
+ return 0;
+ case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
+ case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
+ trans->offset = ((uint32_t)trans->out[0] << 16) |
+ ((uint32_t)trans->out[1] << 8) |
+ ((uint32_t)trans->out[2] << 0);
+ spi_use_out(trans, 3);
+ return 1;
+ default:
+ printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
+ return -1;
+ }
+}
+
+/*
+ * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
+ * below is True) or 0. In case the wait was for the bit(s) to set - write
+ * those bits back, which would cause resetting them.
+ *
+ * Return the last read status value on success or -1 on failure.
+ */
+static int ich_status_poll(u16 bitmask, int wait_til_set)
+{
+ int timeout = 6000; /* This will result in 60 ms */
+ u16 status = 0;
+
+ while (timeout--) {
+ status = readw_(cntlr.status);
+ if (wait_til_set ^ ((status & bitmask) == 0)) {
+ if (wait_til_set)
+ writew_((status & bitmask), cntlr.status);
+ return status;
+ }
+ udelay(10);
+ }
+
+ printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
+ status, bitmask);
+ return -1;
+}
+
+int spi_xfer(struct spi_slave *slave, const void *dout,
+ unsigned int bitsout, void *din, unsigned int bitsin)
+{
+ uint16_t control;
+ int16_t opcode_index;
+ int with_address;
+ int status;
+
+ spi_transaction trans = {
+ dout, bitsout / 8,
+ din, bitsin / 8,
+ 0xff, 0xff, 0
+ };
+
+ /* There has to always at least be an opcode. */
+ if (!bitsout || !dout) {
+ printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
+ return -1;
+ }
+ /* Make sure if we read something we have a place to put it. */
+ if (bitsin != 0 && !din) {
+ printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
+ return -1;
+ }
+ /* Right now we don't support writing partial bytes. */
+ if (bitsout % 8 || bitsin % 8) {
+ printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n");
+ return -1;
+ }
+
+ if (ich_status_poll(SPIS_SCIP, 0) == -1)
+ return -1;
+
+ writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
+
+ spi_setup_type(&trans);
+ if ((opcode_index = spi_setup_opcode(&trans)) < 0)
+ return -1;
+ if ((with_address = spi_setup_offset(&trans)) < 0)
+ return -1;
+
+ if (!ichspi_lock && trans.opcode == 0x06) {
+ /*
+ * Treat Write Enable as Atomic Pre-Op if possible
+ * in order to prevent the Management Engine from
+ * issuing a transaction between WREN and DATA.
+ */
+ writew_(trans.opcode, cntlr.preop);
+ return 0;
+ }
+
+ /* Preset control fields */
+ control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
+
+ /* Issue atomic preop cycle if needed */
+ if (readw_(cntlr.preop))
+ control |= SPIC_ACS;
+
+ if (!trans.bytesout && !trans.bytesin) {
+ /*
+ * This is a 'no data' command (like Write Enable), its
+ * bitesout size was 1, decremented to zero while executing
+ * spi_setup_opcode() above. Tell the chip to send the
+ * command.
+ */
+ writew_(control, cntlr.control);
+
+ /* wait for the result */
+ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
+ if (status == -1)
+ return -1;
+
+ if (status & SPIS_FCERR) {
+ printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
+ return -1;
+ }
+
+ return 0;
+ }
+
+ /*
+ * Check if this is a write command atempting to transfer more bytes
+ * than the controller can handle. Iterations for writes are not
+ * supported here because each SPI write command needs to be preceded
+ * and followed by other SPI commands, and this sequence is controlled
+ * by the SPI chip driver.
+ */
+ if (trans.bytesout > cntlr.databytes) {
+ printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
+ " CONTROLLER_PAGE_LIMIT?\n");
+ return -1;
+ }
+
+ /*
+ * Read or write up to databytes bytes at a time until everything has
+ * been sent.
+ */
+ while (trans.bytesout || trans.bytesin) {
+ uint32_t data_length;
+
+ /* SPI addresses are 24 bit only */
+ writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
+
+ if (trans.bytesout)
+ data_length = min(trans.bytesout, cntlr.databytes);
+ else
+ data_length = min(trans.bytesin, cntlr.databytes);
+
+ /* Program data into FDATA0 to N */
+ if (trans.bytesout) {
+ write_reg(trans.out, cntlr.data, data_length);
+ spi_use_out(&trans, data_length);
+ if (with_address)
+ trans.offset += data_length;
+ }
+
+ /* Add proper control fields' values */
+ control &= ~((cntlr.databytes - 1) << 8);
+ control |= SPIC_DS;
+ control |= (data_length - 1) << 8;
+
+ /* write it */
+ writew_(control, cntlr.control);
+
+ /* Wait for Cycle Done Status or Flash Cycle Error. */
+ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
+ if (status == -1)
+ return -1;
+
+ if (status & SPIS_FCERR) {
+ printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
+ return -1;
+ }
+
+ if (trans.bytesin) {
+ read_reg(cntlr.data, trans.in, data_length);
+ spi_use_in(&trans, data_length);
+ if (with_address)
+ trans.offset += data_length;
+ }
+ }
+
+ /* Clear atomic preop now that xfer is done */
+ writew_(0, cntlr.preop);
+
+ return 0;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 17:25:54 +0000