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-rw-r--r--src/mainboard/asus/p8z77-m_pro/Kconfig48
-rw-r--r--src/mainboard/asus/p8z77-m_pro/Kconfig.name17
-rw-r--r--src/mainboard/asus/p8z77-m_pro/Makefile.inc19
-rw-r--r--src/mainboard/asus/p8z77-m_pro/acpi/ec.asl1
-rw-r--r--src/mainboard/asus/p8z77-m_pro/acpi/platform.asl24
-rw-r--r--src/mainboard/asus/p8z77-m_pro/acpi/superio.asl17
-rw-r--r--src/mainboard/asus/p8z77-m_pro/acpi_tables.c35
-rw-r--r--src/mainboard/asus/p8z77-m_pro/board_info.txt7
-rw-r--r--src/mainboard/asus/p8z77-m_pro/cmos.default24
-rw-r--r--src/mainboard/asus/p8z77-m_pro/cmos.layout185
-rw-r--r--src/mainboard/asus/p8z77-m_pro/data.vbtbin0 -> 3902 bytes
-rw-r--r--src/mainboard/asus/p8z77-m_pro/devicetree.cb109
-rw-r--r--src/mainboard/asus/p8z77-m_pro/dsdt.asl43
-rw-r--r--src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads31
-rw-r--r--src/mainboard/asus/p8z77-m_pro/gpio.c198
-rw-r--r--src/mainboard/asus/p8z77-m_pro/hda_verb.c57
-rw-r--r--src/mainboard/asus/p8z77-m_pro/mainboard.c30
-rw-r--r--src/mainboard/asus/p8z77-m_pro/romstage.c193
18 files changed, 1038 insertions, 0 deletions
diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig b/src/mainboard/asus/p8z77-m_pro/Kconfig
new file mode 100644
index 0000000000..8d29a9bc21
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/Kconfig
@@ -0,0 +1,48 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8Z77_M_PRO
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+ select SUPERIO_NUVOTON_NCT6779D
+ select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA
+
+config MAINBOARD_DIR
+ string
+ default "asus/p8z77-m_pro"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P8Z77-M PRO"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif # BOARD_ASUS_P8Z77_M_PRO
diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig.name b/src/mainboard/asus/p8z77-m_pro/Kconfig.name
new file mode 100644
index 0000000000..c492094508
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/Kconfig.name
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_ASUS_P8Z77_M_PRO
+ bool "P8Z77-M PRO"
diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc
new file mode 100644
index 0000000000..0cc398a5e7
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl b/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl
new file mode 100644
index 0000000000..8b13789179
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl
@@ -0,0 +1 @@
+
diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl
new file mode 100644
index 0000000000..3a696211c1
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl
new file mode 100644
index 0000000000..7f1d04c9ba
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c
new file mode 100644
index 0000000000..2592c19a9e
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <option.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Turn off power for USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Turn off power for USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* critical temp that will shutdown the pc == 95C degrees */
+ gnvs->tcrt = 95;
+
+ /* temp to start throttling the cpu == 85C */
+ gnvs->tpsv = 85;
+}
diff --git a/src/mainboard/asus/p8z77-m_pro/board_info.txt b/src/mainboard/asus/p8z77-m_pro/board_info.txt
new file mode 100644
index 0000000000..66e6f0d6f9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P8Z77M_PRO/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8z77-m_pro/cmos.default
new file mode 100644
index 0000000000..725ab9851d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/cmos.default
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=224M
+nmi=Enable
+sata_mode=AHCI
+#usb3_xxxx options are only used with MRC blob, ignored else
+usb3_mode=Enable
+usb3_drv=Enable
+usb3_streams=Enable
diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout
new file mode 100644
index 0000000000..da29d1c10e
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+#400 8 r 0 reserved for century byte
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408 1 e 1 nmi
+
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# -----------------------------------------------------------------
+# coreboot config options: northbridge
+
+# gfx_uma_size
+# Quantity of shared video memory the IGP can use
+#
+416 5 e 7 gfx_uma_size
+
+# -----------------------------------------------------------------
+# coreboot config options: usb3
+
+# usb3_mode
+# Controls how the motherboard's USB3 ports act at boot time
+421 2 e 8 usb3_mode
+
+# usb3_drv
+# Load (or not) pre-OS xHCI USB3 bios driver
+#
+423 1 e 1 usb3_drv
+
+# usb3_streams
+# Streams can provide more speed (as they can use 64Kb packets),
+# but they might cause incompatibilities with some devices.
+#
+424 1 e 1 usb3_streams
+
+# -----------------------------------------------------------------
+# Sandy/Ivy Bridge MRC Scrambler Seed values
+# note: MUST NOT be covered by checksum!
+464 32 r 0 mrc_scrambler_seed
+496 32 r 0 mrc_scrambler_seed_s3
+528 16 r 0 mrc_scrambler_seed_chk
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+544 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+3 0 Fallback
+3 1 Normal
+
+# debug_level
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+# power_on_after_fail
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# sata_mode
+6 0 AHCI
+6 1 Compatible
+
+# gfx_uma_size (Intel IGP Video RAM size)
+7 0 32M
+7 1 64M
+7 2 96M
+7 3 128M
+7 4 160M
+7 5 192M
+7 6 224M
+7 7 256M
+7 8 288M
+7 9 320M
+7 10 352M
+7 11 384M
+7 12 416M
+7 13 448M
+7 14 480M
+7 15 512M
+7 16 544M
+7 17 576M
+7 18 608M
+7 19 640M
+7 20 672M
+7 21 704M
+7 22 736M
+7 23 768M
+7 24 800M
+7 25 832M
+7 26 864M
+7 27 896M
+7 28 928M
+7 29 960M
+7 30 992M
+
+# usb3_mode
+# Disable = Use the port always as USB 2.0 for compatibility
+# Enable = Use the port always as USB 3.0 for speed
+# Auto = Initialize the port as USB 2.0, until the OS loads
+# xHCI USB 3.0 driver
+# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
+# and the computer is reset, keep the USB 3.0 mode.
+#
+8 0 Disable
+8 1 Enable
+8 2 Auto
+8 3 SmartAuto
+
+# -----------------------------------------------------------------
+# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
+# <bit where to start storing checksum[must be 16bits-aligned]>
+checksums
+
+checksum 392 431 544
diff --git a/src/mainboard/asus/p8z77-m_pro/data.vbt b/src/mainboard/asus/p8z77-m_pro/data.vbt
new file mode 100644
index 0000000000..34679b36a9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb
new file mode 100644
index 0000000000..4f5e5bf9bb
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb
@@ -0,0 +1,109 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.ndid" = "3"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1043 0x84ca inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "gen4_dec" = "0x0000ff29"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
+ register "sata_port_map" = "0x3f" # Enable the six SATA ports
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI 2
+ device pci 1b.0 on end # High Definition Audio controller
+ device pci 1c.0 on end # PCIe Root Port 1 PCIEX_16_3
+ device pci 1c.1 on end # PCIe Root Port 6 RTL8111F
+ device pci 1c.2 off end # PCIe Port 3 unused
+ device pci 1c.3 off end # PCIe Port 4 unused
+ device pci 1c.4 off end # PCIe Port 5 unused
+ device pci 1c.5 on end # PCIe Root Port 7 ASM1042 USB3
+ device pci 1c.6 on end # PCIe Root Port 8 ASM1061 eSATA
+ device pci 1c.7 off end # PCIe Port 8 unused
+ device pci 1d.0 on end # USB2 EHCI 1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 off end # UART A
+ device pnp 2e.3 on # UART B, IR
+ io 0x60 = 0x2f8 # COM2 address
+ end
+ device pnp 2e.5 on # PS2 KBC
+ io 0x60 = 0x0060 # KBC1 base
+ io 0x62 = 0x0064 # KBC2 base
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+
+ # KBC 12Mhz/A20 speed/sw KBRST
+ drq 0xf0 = 0x82
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on end # GPIOs 6-8
+ device pnp 2e.8 off end # WDT1 GPIO 0-1
+ device pnp 2e.9 off end # GPIO 1-8
+ device pnp 2e.a on # ACPI
+ drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
+ drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
+ end
+ device pnp 2e.b off end # HWM, LED
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f on # GPIO PP/OD
+ drq 0xe6 = 0x7f # GP7 PP
+ end
+ device pnp 2e.14 on end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
+ end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM module
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl
new file mode 100644
index 0000000000..89ad30c997
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads
new file mode 100644
index 0000000000..f9dd430d24
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads
@@ -0,0 +1,31 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1, -- DVI-D port on rear
+ HDMI3, -- real HDMI port on rear
+ Analog, -- VGA port on rear
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8z77-m_pro/gpio.c
new file mode 100644
index 0000000000..c8842159d3
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/gpio.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c
new file mode 100644
index 0000000000..4fd3fcc5e3
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */
+ 0x10438436, /* Subsystem ID */
+
+ 0x0000000f, /* Number of 4 dword sets */
+ /* Subsystem ID */
+ AZALIA_SUBVENDOR(0x0, 0x10438436),
+
+ AZALIA_PIN_CFG(0x0, 0x11, 0x99430140),
+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0x0, 0x17, 0x01012014),
+ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850),
+ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f),
+ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601),
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130),
+ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* Subsystem ID */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8z77-m_pro/mainboard.c b/src/mainboard/asus/p8z77-m_pro/mainboard.c
new file mode 100644
index 0000000000..6cb41cc738
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/mainboard.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT,
+ 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable
+};
diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c
new file mode 100644
index 0000000000..b5593ec23c
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m_pro/romstage.c
@@ -0,0 +1,193 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#include <option.h>
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/pei_data.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF1_LPC_EN | CNF2_LPC_EN |
+ KBC_LPC_EN | COMB_LPC_EN);
+
+ /* Set COMB/COM2 IO range to 2F8h-2FFh */
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* {enable, current, oc_pin} */
+ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
+ { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
+ { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
+ { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
+ { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
+ { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
+ { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
+ { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
+ { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
+ { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
+ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
+ { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
+ { 0, 2, 5 }, /* Port 12: Unused. Asus propietary DEBUG_PORT ??? */
+ { 0, 2, 6 } /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+ /* Setup COM/UART */
+ nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+ /* TODO / FIXME: Setup Multifuncion/SIO pins for COM */
+
+ pnp_set_logical_device(SERIAL_DEV);
+ nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /*
+ * USB3 mode:
+ * 0 = Disable: work always as USB 2.0(ehci)
+ * 1 = Enable: work always as USB 3.0(xhci)
+ * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
+ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
+ * and reboots, it will keep the USB3.0 speed
+ */
+ int usb3_mode = 1;
+ get_option(&usb3_mode, "usb3_mode");
+ usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
+
+ /* Load USB3 pre-OS xHCI driver */
+ int usb3_drv = 1;
+ get_option(&usb3_drv, "usb3_drv");
+ usb3_drv &= 0x1; /* ensure it's 0/1 only */
+
+ /* Use USB3 xHCI streams */
+ int usb3_streams = 1;
+ get_option(&usb3_streams, "usb3_streams");
+ usb3_streams &= 0x1; /* ensure it's 0/1 only */
+
+ struct pei_data pd = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 1, /* 0=Mobile, 1=Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
+ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
+ .dimm_channel0_disabled = 0, /* Both DIMM enabled */
+ .dimm_channel1_disabled = 0, /* Both DIMM enabled */
+ .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
+ .usb_port_config = {
+ /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 1, 0x0080 }, /* USB3 ETH top connector */
+ { 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
+ { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */
+ },
+ .usb3 = {
+ /* 0=Disable; 1=Enable (start at USB3 speed)
+ * 2=Auto (start as USB2 speed until OS loads)
+ * 3=Smart Auto (like Auto but keep speed on reboot)
+ */
+ usb3_mode,
+ /* 4 bit switch mask. 0=not switchable, 1=switchable
+ * Means once it's loaded the OS, it can swap ports
+ * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+ */
+ 0xf,
+ usb3_drv, /* 1=Load xHCI pre-OS drv */
+ /* 0=Don't use xHCI streams for better compatibility
+ * 1=use xHCI streams for better speed
+ */
+ usb3_streams
+ },
+ /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */
+ .ddr3lv_support = 1,
+ /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
+ * but might cause some system inestability !
+ */
+ .pcie_init = 1,
+ /* Command Rate. 0=Auto; 1=1N; 2=2N.
+ * Leave it always at Auto for compatibility & stability
+ */
+ .nmode = 0,
+ /* DDR refresh rate. 0=Auto based on DRAM's temperature;
+ * 1=Normal rate for speed; 2=Double rate for stability
+ */
+ .ddr_refresh_rate_config = 0
+ };
+
+ /* copy the data to output PEI */
+ *pei_data = pd;
+}