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-rw-r--r--src/commonlib/Makefile.inc1
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig1
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/api.h4
-rw-r--r--src/drivers/intel/fsp2_0/silicon_init.c47
-rw-r--r--src/soc/intel/apollolake/chip.c7
5 files changed, 47 insertions, 13 deletions
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index be22e0097d..3c375d5674 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -12,6 +12,7 @@ smm-y += region.c
postcar-y += region.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
bootblock-y += cbfs.c
verstage-y += cbfs.c
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 6cfacad6bb..45679f78bf 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -1,5 +1,6 @@
config PLATFORM_USES_FSP2_0
bool
+ select UEFI_2_4_BINDING
help
Include FSP 2.0 wrappers and functionality
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 510163d77d..31137cc8f5 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -14,7 +14,6 @@
#define _FSP2_0_API_H_
#include <stddef.h>
-#include <memrange.h>
#include <fsp/info_header.h>
#include <soc/fsp/FspmUpd.h>
#include <soc/fsp/FspsUpd.h>
@@ -59,7 +58,7 @@ enum fsp_notify_phase {
/* Main FSP stages */
enum fsp_status fsp_memory_init(bool s3wake);
-enum fsp_status fsp_silicon_init(struct range_entry *r);
+enum fsp_status fsp_silicon_init(void);
enum fsp_status fsp_notify(enum fsp_notify_phase phase);
/* Callbacks for updating stage-specific parameters */
@@ -87,7 +86,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
*
*
* ### fsp_silicon_init():
- * - r: memory range that the binary is allowed to be loaded into
*
* This function is responsible for loading and executing the silicon
* initialization code from the FSP-S binary. It expects this binary to reside
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index f1deed78d8..83245b8bdb 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -12,9 +12,12 @@
#include <arch/cpu.h>
#include <cbfs.h>
+#include <cbmem.h>
+#include <commonlib/fsp.h>
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <program_loading.h>
#include <string.h>
#include <timestamp.h>
@@ -53,11 +56,47 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr)
return status;
}
-enum fsp_status fsp_silicon_init(struct range_entry *range)
+enum fsp_status fsp_silicon_init(void)
{
- /* Load FSP-S and save FSP header. We will need it for Notify */
- if (fsp_load_binary(&fsps_hdr, CONFIG_FSP_S_CBFS, range) != CB_SUCCESS)
+ struct fsp_header *hdr = &fsps_hdr;
+ struct cbfsf file_desc;
+ struct region_device rdev;
+ const char *name = CONFIG_FSP_S_CBFS;
+ void *dest;
+ size_t size;
+
+ if (cbfs_boot_locate(&file_desc, name, NULL)) {
+ printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
+ return FSP_NOT_FOUND;
+ }
+
+ cbfs_file_data(&rdev, &file_desc);
+
+ /* Load and relocate into CBMEM. */
+ size = region_device_sz(&rdev);
+ dest = cbmem_add(CBMEM_ID_REFCODE, size);
+
+ if (dest == NULL) {
+ printk(BIOS_ERR, "Could not add FSPS to CBMEM.\n");
+ return FSP_NOT_FOUND;
+ }
+
+ if (rdev_readat(&rdev, dest, 0, size) < 0)
+ return FSP_NOT_FOUND;
+
+ if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) {
+ printk(BIOS_ERR, "Unable to relocate FSPS.\n");
+ return FSP_NOT_FOUND;
+ }
+
+ /* Create new region device in memory after relocation. */
+ rdev_chain(&rdev, &addrspace_32bit.rdev, (uintptr_t)dest, size);
+
+ if (fsp_validate_component(hdr, &rdev) != CB_SUCCESS)
return FSP_NOT_FOUND;
- return do_silicon_init(&fsps_hdr);
+ /* Signal that FSP component has been loaded. */
+ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
+
+ return do_silicon_init(hdr);
}
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index accc1bb1d0..3a6e90e5e2 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -25,7 +25,6 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
-#include <memrange.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
@@ -192,7 +191,6 @@ static void pcie_override_devicetree_after_silicon_init(void)
static void soc_init(void *data)
{
- struct range_entry range;
struct global_nvs_t *gnvs;
/* Save VBT info and mapping */
@@ -203,10 +201,7 @@ static void soc_init(void *data)
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
- /* TODO: tigten this resource range */
- /* TODO: fix for S3 resume, as this would corrupt OS memory */
- range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
- fsp_silicon_init(&range);
+ fsp_silicon_init();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);