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-rw-r--r--src/mainboard/bifferos/bifferboard/Kconfig8
-rw-r--r--src/mainboard/bifferos/bifferboard/devicetree.cb6
-rw-r--r--src/northbridge/rdc/r8610/Kconfig3
-rw-r--r--src/soc/rdc/r8610/Kconfig (renamed from src/southbridge/rdc/r8610/Kconfig)12
-rw-r--r--src/soc/rdc/r8610/Makefile.inc (renamed from src/northbridge/rdc/r8610/Makefile.inc)4
-rw-r--r--src/soc/rdc/r8610/bootblock.c (renamed from src/southbridge/rdc/r8610/bootblock.c)10
-rw-r--r--src/soc/rdc/r8610/northbridge.c (renamed from src/northbridge/rdc/r8610/northbridge.c)6
-rw-r--r--src/soc/rdc/r8610/r8610.c (renamed from src/southbridge/rdc/r8610/r8610.c)8
-rw-r--r--src/southbridge/rdc/r8610/Makefile.inc20
9 files changed, 31 insertions, 46 deletions
diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig
index cf08ac8b9a..c65b02ffa2 100644
--- a/src/mainboard/bifferos/bifferboard/Kconfig
+++ b/src/mainboard/bifferos/bifferboard/Kconfig
@@ -2,14 +2,8 @@ if BOARD_BIFFEROS_BIFFERBOARD
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
- select ROMCC
select BOARD_ROMSIZE_KB_128
- select NORTHBRIDGE_RDC_R8610
- select SOUTHBRIDGE_RDC_R8610
+ select SOC_RDC_R8610
config MAINBOARD_DIR
string
diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb
index 09dde33517..a64b138cb0 100644
--- a/src/mainboard/bifferos/bifferboard/devicetree.cb
+++ b/src/mainboard/bifferos/bifferboard/devicetree.cb
@@ -1,8 +1,6 @@
-chip northbridge/rdc/r8610
+chip soc/rdc/r8610
device domain 0 on
device pci 0.0 on end
- chip southbridge/rdc/r8610 # Southbridge
- device pci 7.0 on end # SB
- end
+ device pci 7.0 on end # SB
end
end
diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig
deleted file mode 100644
index e93a3e65b9..0000000000
--- a/src/northbridge/rdc/r8610/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-config NORTHBRIDGE_RDC_R8610
- bool
- select LATE_CBMEM_INIT
diff --git a/src/southbridge/rdc/r8610/Kconfig b/src/soc/rdc/r8610/Kconfig
index 0a2a80bba0..d849f9c9d2 100644
--- a/src/southbridge/rdc/r8610/Kconfig
+++ b/src/soc/rdc/r8610/Kconfig
@@ -13,10 +13,16 @@
## GNU General Public License for more details.
##
-config SOUTHBRIDGE_RDC_R8610
+config SOC_RDC_R8610
bool
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ROMCC
+ select LATE_CBMEM_INIT
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
- default "southbridge/rdc/r8610/bootblock.c"
- depends on SOUTHBRIDGE_RDC_R8610
+ default "soc/rdc/r8610/bootblock.c"
+ depends on SOC_RDC_R8610
diff --git a/src/northbridge/rdc/r8610/Makefile.inc b/src/soc/rdc/r8610/Makefile.inc
index a5afca6ff4..652562cb96 100644
--- a/src/northbridge/rdc/r8610/Makefile.inc
+++ b/src/soc/rdc/r8610/Makefile.inc
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -14,8 +15,9 @@
## GNU General Public License for more details.
##
-ifeq ($(CONFIG_NORTHBRIDGE_RDC_R8610),y)
+ifeq ($(CONFIG_SOC_RDC_R8610),y)
ramstage-y += northbridge.c
+ramstage-y += r8610.c
endif
diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/soc/rdc/r8610/bootblock.c
index 40c4fa71f3..0dc776ea93 100644
--- a/src/southbridge/rdc/r8610/bootblock.c
+++ b/src/soc/rdc/r8610/bootblock.c
@@ -16,9 +16,11 @@
#include <arch/io.h>
#include <device/pci_def.h>
-static void bootblock_southbridge_init(void) {
- uint32_t tmp;
- tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40);
+static void bootblock_southbridge_init(void)
+{
+ uint32_t tmp;
+
+ tmp = pci_read_config32(PCI_DEV(0, 7, 0), 0x40);
/* decode all flash ranges */
- pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000);
+ pci_write_config32(PCI_DEV(0, 7, 0), 0x40, tmp | 0x07ff0000);
}
diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/soc/rdc/r8610/northbridge.c
index b536626936..00aa0d419a 100644
--- a/src/northbridge/rdc/r8610/northbridge.c
+++ b/src/soc/rdc/r8610/northbridge.c
@@ -88,9 +88,11 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current)
return len;
}
-static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current)
+static int rdc_get_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
{
int len;
+
len = rdc_get_smbios_data16(*handle, current);
*handle += 1;
return len;
@@ -110,8 +112,8 @@ static struct device_operations pci_domain_ops = {
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ /* Set the operations if it is a special bus type */
dev->ops = &pci_domain_ops;
}
}
diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/soc/rdc/r8610/r8610.c
index f53ce6612d..e34a29940e 100644
--- a/src/southbridge/rdc/r8610/r8610.c
+++ b/src/soc/rdc/r8610/r8610.c
@@ -45,7 +45,9 @@ static void r8610_init(struct device *dev)
/* Set serial base */
pci_write_config32(dev, 0x54, 0x3f8);
- /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
+ /* serial IRQ disable, LPC disable,
+ * COM2 goes to LPC, internal UART for COM1
+ */
pci_write_config32(dev, 0x50, 0x84101012);
/* Enable internal Port92, enable chipselect for flash */
@@ -55,7 +57,9 @@ static void r8610_init(struct device *dev)
/* buffer strength SB pins */
pci_write_config32(dev, 0x5c, 0x2315);
- /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */
+ /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9,
+ * INTC 9, INTB 12, INTA INT10
+ */
pci_write_config32(dev, 0x58, 0xdf0311b3);
/* USB PHY control */
diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc
deleted file mode 100644
index a4069e9688..0000000000
--- a/src/southbridge/rdc/r8610/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOUTHBRIDGE_RDC_R8610),y)
-
-ramstage-y += r8610.c
-
-endif