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-rw-r--r--src/cpu/amd/agesa/family15tn/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c16
-rw-r--r--src/cpu/x86/smm/smmhandler.S8
-rw-r--r--src/cpu/x86/smm/smmrelocate.S3
-rw-r--r--src/include/cpu/amd/amdfam15.h2
5 files changed, 29 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index a5a707167f..19a2f0f298 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-y += chip_name.c
ramstage-y += model_15_init.c
subdirs-y += ../../mtrr
+subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index f396201181..467a3012df 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
@@ -43,6 +44,7 @@ static void model_15_init(device_t dev)
u8 i;
msr_t msr;
int msrno;
+ unsigned int cpu_idx;
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@@ -110,6 +112,20 @@ static void model_15_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ cpu_idx = cpu_info()->index;
+ printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
+
+ /* Set SMM base address for this CPU */
+ msr = rdmsr(MSR_SMM_BASE);
+ msr.lo = SMM_BASE - (cpu_idx * 0x400);
+ wrmsr(MSR_SMM_BASE, msr);
+
+ /* Enable the SMM memory window */
+ msr = rdmsr(MSR_SMM_MASK);
+ msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
+ wrmsr(MSR_SMM_MASK, msr);
+ }
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 774088e1f2..484b643017 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -105,6 +105,14 @@ smm_handler_start:
movl (%esi), %ecx
shr $24, %ecx
+ /* This is an ugly hack, and we should find a way to read the CPU index
+ * without relying on the LAPIC ID.
+ */
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
+ /* LAPIC IDs start from 0x10; map that to the proper core index */
+ subl $0x10, %ecx
+#endif
+
/* calculate stack offset by multiplying the APIC ID
* by 1024 (0x400), and save that offset in ebp.
*/
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 71f74e757f..bdc977190b 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -23,7 +23,8 @@
#define __PRE_RAM__
/* On AMD's platforms we can set SMBASE by writing an MSR */
-#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \
+ && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
index 0c2cf7bde7..67e7cee5df 100644
--- a/src/include/cpu/amd/amdfam15.h
+++ b/src/include/cpu/amd/amdfam15.h
@@ -23,6 +23,8 @@
#include <cpu/x86/msr.h>
#define MCI_STATUS 0x00000401
+#define MSR_SMM_BASE 0xC0010111
+#define MSR_SMM_MASK 0xC0010113
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f