summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c23
1 files changed, 1 insertions, 22 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index bc9d63826d..6fc4d92662 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -171,32 +171,11 @@ static void check_for_clean_reset(void)
soft_reset();
}
-static void patch_microcode(void)
-{
- const struct microcode *patch;
- u32 current_rev;
- msr_t msr;
-
- patch = intel_microcode_find();
-
- current_rev = read_microcode_rev();
-
- /* If PRMRR/SGX is supported the FIT microcode load step will set
- * msr 0x08b with the Patch revision id one less than the id in the
- * microcode binary. The PRMRR support is indicated in the MSR
- * MTRRCAP[12]. Check for this feature and avoid reloading the
- * same microcode during early cpu initialization.
- */
- msr = rdmsr(MTRR_CAP_MSR);
- if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1))
- intel_update_microcode_from_cbfs();
-}
-
static void bootblock_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
check_for_clean_reset();
enable_rom_caching();
- patch_microcode();
+ intel_update_microcode_from_cbfs();
}