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-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h2
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h2
-rw-r--r--src/soc/intel/skylake/smmrelocate.c4
-rw-r--r--src/soc/intel/skylake/systemagent.c4
4 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 55d0bfd458..6236915c53 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -72,8 +72,6 @@
#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_POWER_CTL 0x1fc
#define MSR_EVICT_CTL 0x2e0
-#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4
-#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
#define IA32_MC0_CTL 0x400
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 4ff4ad2d49..0bd7f3ce60 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -32,6 +32,8 @@
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_LT_LOCK_MEMORY 0x2e7
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_VR_MISC_CONFIG 0x603
#define MSR_VR_MISC_CONFIG2 0x636
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 482107b111..dbe0c9485b 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -50,8 +50,8 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
"Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->uncore_emrr_base.lo,
relo_params->uncore_emrr_mask.lo);
- wrmsr(UNCORE_PRMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base);
- wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask);
}
static void update_save_state(int cpu, uintptr_t curr_smbase,
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index ba7c3075cd..8af995d133 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -69,9 +69,9 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
uint64_t *prmrr_mask)
{
msr_t msr;
- msr = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
+ msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
*prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
- msr = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR);
+ msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
*prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
return 0;
}