4 files changed, 145 insertions, 0 deletions
diff --git a/src/drivers/i2c/rt5663/Kconfig b/src/drivers/i2c/rt5663/Kconfig
new file mode 100644
index 0000000000..51109729fd
--- /dev/null
+++ b/src/drivers/i2c/rt5663/Kconfig
@@ -0,0 +1,4 @@
+config DRIVERS_I2C_RT5663
+	bool
+	default n
+	depends on HAVE_ACPI_TABLES
diff --git a/src/drivers/i2c/rt5663/Makefile.inc b/src/drivers/i2c/rt5663/Makefile.inc
new file mode 100644
index 0000000000..35c566b976
--- /dev/null
+++ b/src/drivers/i2c/rt5663/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_I2C_RT5663) += rt5663.c
diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h
new file mode 100644
index 0000000000..1b367c934f
--- /dev/null
+++ b/src/drivers/i2c/rt5663/chip.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Realtek RT5663 audio codec devicetree bindings
+ */
+struct drivers_i2c_rt5663_config {
+	/* I2C Bus Frequency in Hertz (default 400kHz) */
+	unsigned int bus_speed;
+	/* Identifier for multiple chips */
+	unsigned int uid;
+
+	/* Allow GPIO based interrupt or PIRQ */
+	struct acpi_gpio irq_gpio;
+	struct acpi_irq irq;
+
+	/* Manual offset value to compensate DC offset for L/R channels */
+	uint32_t dc_offset_l_manual;
+	uint32_t dc_offset_r_manual;
+	uint32_t dc_offset_l_manual_mic;
+	uint32_t dc_offset_r_manual_mic;
+};
diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c
new file mode 100644
index 0000000000..e8734dc8c2
--- /dev/null
+++ b/src/drivers/i2c/rt5663/rt5663.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <stdint.h>
+#include <string.h>
+#include "chip.h"
+
+#define RT5663_ACPI_NAME	"RT53"
+#define RT5663_ACPI_HID		"10EC5663"
+
+#define RT5663_DP_INT(key, val) \
+	acpi_dp_add_integer(dp, "realtek," key, (val))
+
+static void rt5663_fill_ssdt(struct device *dev)
+{
+	struct drivers_i2c_rt5663_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	struct acpi_i2c i2c = {
+		.address = dev->path.i2c.device,
+		.mode_10bit = dev->path.i2c.mode_10bit,
+		.speed = config->bus_speed ? : I2C_SPEED_FAST,
+		.resource = scope,
+	};
+	struct acpi_dp *dp;
+
+	if (!dev->enabled || !scope)
+		return;
+
+	/* Device */
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+	acpigen_write_name_string("_HID", RT5663_ACPI_HID);
+	acpigen_write_name_integer("_UID", config->uid);
+	acpigen_write_name_string("_DDN", dev->chip_ops->name);
+	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
+
+	/* Resources */
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	acpi_device_write_i2c(&i2c);
+	/* Allow either GpioInt() or Interrupt() */
+	if (config->irq_gpio.pin_count)
+		acpi_device_write_gpio(&config->irq_gpio);
+	else
+		acpi_device_write_interrupt(&config->irq);
+	acpigen_write_resourcetemplate_footer();
+
+	/* Device Properties */
+	dp = acpi_dp_new_table("_DSD");
+	if (config->irq_gpio.pin_count)
+		acpi_dp_add_gpio(dp, "irq-gpios", acpi_device_path(dev), 0, 0,
+			 config->irq_gpio.polarity == ACPI_GPIO_ACTIVE_LOW);
+	RT5663_DP_INT("dc_offset_l_manual", config->dc_offset_l_manual);
+	RT5663_DP_INT("dc_offset_r_manual", config->dc_offset_r_manual);
+	RT5663_DP_INT("dc_offset_l_manual_mic", config->dc_offset_l_manual_mic);
+	RT5663_DP_INT("dc_offset_r_manual_mic", config->dc_offset_r_manual_mic);
+	acpi_dp_write(dp);
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+
+	printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev),
+			dev->chip_ops->name, dev->path.i2c.device);
+}
+
+static const char *rt5663_acpi_name(struct device *dev)
+{
+	return RT5663_ACPI_NAME;
+}
+
+static struct device_operations rt5663_ops = {
+	.read_resources			= DEVICE_NOOP,
+	.set_resources			= DEVICE_NOOP,
+	.enable_resources		= DEVICE_NOOP,
+	.acpi_name			= &rt5663_acpi_name,
+	.acpi_fill_ssdt_generator	= &rt5663_fill_ssdt,
+};
+
+static void rt5663_enable(struct device *dev)
+{
+	dev->ops = &rt5663_ops;
+}
+
+struct chip_operations drivers_i2c_rt5663_ops = {
+	CHIP_NAME("Realtek RT5663 Codec")
+	.enable_dev = &rt5663_enable
+};