summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/l520/romstage.c14
-rw-r--r--src/mainboard/lenovo/s230u/romstage.c17
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h2
3 files changed, 19 insertions, 14 deletions
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 0f6ffede3d..89bc8ef787 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -25,11 +25,15 @@
void pch_enable_lpc(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ /* EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse, LPT */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ LPT_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index 7e002d4715..f4241dbba5 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -32,18 +32,17 @@
void pch_enable_lpc(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */
pci_write_config32(
- PCI_DEV(0, 0x1f, 0), 0x98,
+ PCH_LPC_DEV, LGMR,
CONFIG_EC_BASE_ADDRESS | 1);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0);
+ pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0);
/* Enable external USB port power. */
if (IS_ENABLED(CONFIG_USBDEBUG))
@@ -53,7 +52,7 @@ void pch_enable_lpc(void)
void mainboard_rcba_config(void)
{
/* Disable devices. */
- RCBA32(0x3414) = 0x00000020;
+ RCBA32(BUC) = 0x00000020;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 },
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 66f5727e61..e234ca0036 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -188,6 +188,8 @@ int rtc_failure(void);
#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+#define LGMR 0x98 /* LPC Generic Memory Range */
+#define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */
/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)