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-rw-r--r--src/soc/intel/broadwell/acpi/globalnvs.asl2
-rw-r--r--src/soc/intel/broadwell/acpi/lpc.asl23
-rw-r--r--src/soc/intel/broadwell/include/soc/nvs.h4
3 files changed, 3 insertions, 26 deletions
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index 4ba384a4af..9bddbc212c 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -53,7 +53,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TCRT, 8, // 0x10 - Critical Threshold
TPSV, 8, // 0x11 - Passive Threshold
TMAX, 8, // 0x12 - CPU Tj_max
- TPMP, 8, // 0x13 - TPM Present
+ , 8, // 0x13 - Unused
S5U0, 8, // 0x14 - Enable USB in S5
S3U0, 8, // 0x15 - Enable USB in S3
S33G, 8, // 0x16 - Enable 3G in S3
diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl
index ae634a3fd6..2b574f756d 100644
--- a/src/soc/intel/broadwell/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/acpi/lpc.asl
@@ -201,29 +201,6 @@ Device (LPCB)
})
}
- Device (TPM) // Trusted Platform Module
- {
- Name (_HID, EISAID("IFX0102"))
- Name (_CID, 0x310cd041)
- Name (_UID, 1)
-
- Method (_STA, 0)
- {
- If (TPMP) {
- Return (0xf)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_CRS, ResourceTemplate() {
- IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
- IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
- Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
- IRQ (Edge, Activehigh, Exclusive) { 6 }
- })
- }
-
#include "gpio.asl"
#include "irqlinks.asl"
#include <acpi/ec.asl>
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 195dd43c3e..2f835c88ac 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -44,7 +44,7 @@ typedef struct {
u8 tcrt; /* 0x10 - Critical Threshold */
u8 tpsv; /* 0x11 - Passive Threshold */
u8 tmax; /* 0x12 - CPU Tj_max */
- u8 tpmp; /* 0x13 - TPM Present */
+ u8 unused1; /* 0x13 - Unused */
u8 s5u0; /* 0x14 - Enable USB in S5 */
u8 s3u0; /* 0x15 - Enable USB in S3 */
u8 s33g; /* 0x16 - Enable 3G in S3 */
@@ -54,7 +54,7 @@ typedef struct {
u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
u32 gpei; /* 0x25 - 0x28 - GPE wake status bit */
- u8 rsvd3[215];
+ u8 unused[215];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;