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-rw-r--r--src/soc/rockchip/rk3288/clock.c2
-rw-r--r--src/soc/rockchip/rk3288/include/soc/clock.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 31901e7ec6..b6bafe81ae 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -79,9 +79,11 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
+static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2);
static const struct pll_div *apll_cfgs[] = {
[APLL_1800_MHZ] = &apll_1800_cfg,
[APLL_1392_MHZ] = &apll_1392_cfg,
+ [APLL_600_MHZ] = &apll_600_cfg,
};
/*******************PLL CON0 BITS***************************/
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index 3fccecb8f2..995f4e51c2 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -31,6 +31,7 @@
enum apll_frequencies {
APLL_1800_MHZ,
APLL_1392_MHZ,
+ APLL_600_MHZ,
};
/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */