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-rw-r--r--src/northbridge/intel/fsp_sandybridge/gma.c27
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/lpc.c6
-rw-r--r--src/southbridge/intel/fsp_i89xx/lpc.c6
3 files changed, 27 insertions, 12 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index affbbc69bb..0034b06a23 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -19,6 +19,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <southbridge/intel/fsp_bd82x6x/nvs.h>
+#include <cbmem.h>
#include "chip.h"
#include "northbridge.h"
@@ -80,6 +82,30 @@ static void gma_ssdt(device_t device)
drivers_intel_gma_displays_ssdt_generate(gfx);
}
+static unsigned long
+gma_write_acpi_tables(struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ igd_opregion_t *opregion;
+ global_nvs_t *gnvs;
+
+ // FIXME: Replace by common VBT implementation writing to current
+ opregion = igd_make_opregion();
+ if (opregion) {
+ /* GNVS has been already set up */
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+ if (gnvs) {
+ /* IGD OpRegion Base Address */
+ gnvs->aslb = (u32)(uintptr_t)opregion;
+ } else {
+ printk(BIOS_ERR, "Error: GNVS table not found.\n");
+ }
+ }
+
+ return current;
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -93,6 +119,7 @@ static struct device_operations gma_func0_ops = {
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
+ .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short gma_ids[] = {
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index c2dea6bca3..963359f873 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -589,10 +589,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -600,8 +596,6 @@ static void southbridge_inject_dsdt(device_t dev)
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 7ebe6e4a11..5ba296956c 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -501,10 +501,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -512,8 +508,6 @@ static void southbridge_inject_dsdt(device_t dev)
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));