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-rw-r--r--src/arch/x86/include/arch/io.h9
-rw-r--r--src/include/device/device.h2
2 files changed, 6 insertions, 5 deletions
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index b6d82f9275..d5cdf350ba 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -4,6 +4,11 @@
#include <stdint.h>
#include <rules.h>
+/* FIXME: Sources for romstage still use device_t. */
+/* Use pci_devfn_t or pnp_devfn_t instead */
+typedef u32 pci_devfn_t;
+typedef u32 pnp_devfn_t;
+
/*
* This file contains the definitions for the x86 IO instructions
* inb/inw/inl/outb/outw/outl and the "string versions" of the same
@@ -218,11 +223,9 @@ static inline int log2f(int value)
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
/* FIXME: Sources for romstage still use device_t. */
+/* Use pci_devfn_t or pnp_devfn_t instead */
typedef u32 device_t;
-typedef u32 pci_devfn_t;
-typedef u32 pnp_devfn_t;
-
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
diff --git a/src/include/device/device.h b/src/include/device/device.h
index cf4cb8c84c..3810716057 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -18,8 +18,6 @@ struct device;
#ifndef __SIMPLE_DEVICE__
typedef struct device * device_t;
-typedef u32 pci_devfn_t;
-typedef u32 pnp_devfn_t;
struct pci_operations;
struct pci_bus_operations;
struct smbus_bus_operations;