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-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_common.h26
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs.h11
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h11
3 files changed, 28 insertions, 20 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h
new file mode 100644
index 0000000000..6d27f89549
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/gpio_common.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_
+#define _SOC_CANNONLAKE_GPIO_COMMON_H_
+
+#define GPIORXSTATE_MASK 0x1
+#define GPIORXSTATE_SHIFT 1
+#define GPIOTXSTATE_MASK 0x1
+#define GPIOPADMODE_MASK 0xC00
+#define GPIOPADMODE_SHIFT 10
+#define GPIOTXBUFDIS_MASK 0x100
+#define GPIORXBUFDIS_MASK 0x200
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 3399526cff..8a944b1b48 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -19,9 +19,9 @@
#ifndef __ACPI__
#include <stddef.h>
#endif
+#include <soc/gpio_common.h>
#include <soc/gpio_soc_defs.h>
-
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
#define NUM_GPIO_COMx_GPI_REGS(n) \
@@ -250,13 +250,4 @@
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600
-#define GPIORXSTATE_MASK 0x1
-#define GPIORXSTATE_SHIFT 1
-#define GPIOTXSTATE_MASK 0x1
-#define GPIOPADMODE_MASK 0xC00
-#define GPIOPADMODE_SHIFT 10
-#define GPIOTXBUFDIS_MASK 0x100
-#define GPIOTXBUFDIS_SHIFT 8
-#define GPIORXBUFDIS_MASK 0x200
-#define GPIORXBUFDIS_SHIFT 9
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
index c7f3c816ba..e77dbf88cf 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
@@ -19,9 +19,9 @@
#ifndef __ACPI__
#include <stddef.h>
#endif
+#include <soc/gpio_common.h>
#include <soc/gpio_soc_defs_cnp_h.h>
-
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
#define NUM_GPIO_COMx_GPI_REGS(n) \
@@ -324,13 +324,4 @@
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600
-#define GPIORXSTATE_MASK 0x1
-#define GPIORXSTATE_SHIFT 1
-#define GPIOTXSTATE_MASK 0x1
-#define GPIOPADMODE_MASK 0xC00
-#define GPIOPADMODE_SHIFT 10
-#define GPIOTXBUFDIS_MASK 0x100
-#define GPIOTXBUFDIS_SHIFT 8
-#define GPIORXBUFDIS_MASK 0x200
-#define GPIORXBUFDIS_SHIFT 9
#endif