diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/fizz/Kconfig | 29 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 22 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/mainboard.c | 15 |
3 files changed, 3 insertions, 63 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index b1f353d53d..ce5c8bdd04 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -15,7 +15,9 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 select SOC_INTEL_KABYLAKE - select FIZZ_USE_SPI_TPM + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM + select TPM2 select GENERIC_SPD_BIN select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE @@ -29,16 +31,7 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN -config DRIVER_TPM_I2C_BUS - depends on FIZZ_USE_I2C_TPM - default 0x1 - -config DRIVER_TPM_I2C_ADDR - depends on FIZZ_USE_I2C_TPM - default 0x50 - config DRIVER_TPM_SPI_BUS - depends on FIZZ_USE_SPI_TPM default 0x1 config GBB_HWID @@ -70,22 +63,6 @@ config DIMM_SPD_SIZE int default 512 -# Select this option to enable use of cr50 I2C TPM on fizz. -config FIZZ_USE_I2C_TPM - bool - default n - select I2C_TPM - select MAINBOARD_HAS_I2C_TPM_CR50 - select TPM2 - -# Select this option to enable use of cr50 I2C TPM on fizz. -config FIZZ_USE_SPI_TPM - bool - default n - select MAINBOARD_HAS_SPI_TPM_CR50 - select SPI_TPM - select TPM2 - config TPM_TIS_ACPI_INTERRUPT int default 64 # GPE0_DW2_00 (GPP_E0) diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index d54a1fed0f..e6dc3a751b 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -92,7 +92,6 @@ static const struct pad_config gpio_table[] = { /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, @@ -101,12 +100,6 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -#else -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -#endif /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ /* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */ @@ -142,15 +135,8 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SDA */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SCL */ -#else /* I2C1_SDA */ PAD_CFG_NC(GPP_C18), /* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -#endif /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ @@ -275,7 +261,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, @@ -284,13 +269,6 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -#endif -#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SDA */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SCL */ -#endif /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 54d7c4c103..ce60283eaf 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -132,7 +132,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { - device_t tpm; device_t root = SA_DEV_ROOT; config_t *conf = root->chip_info; @@ -140,20 +139,6 @@ static void mainboard_enable(device_t dev) dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; - - /* Disable unused interface for TPM. */ - if (!IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM)) { - tpm = PCH_DEV_GSPI0; - if (tpm) - tpm->enabled = 0; - } - - if (!IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)) { - tpm = PCH_DEV_I2C1; - if (tpm) - tpm->enabled = 0; - } - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } |