summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/drivers/uart/pl011.c19
-rw-r--r--src/drivers/uart/pl011.h94
2 files changed, 106 insertions, 7 deletions
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index 709320b288..e690a9afb5 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright 2018-present Facebook, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -13,13 +14,10 @@
* GNU General Public License for more details.
*/
+#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
-
-static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data)
-{
- *uart_base = (unsigned int)data;
-}
+#include <drivers/uart/pl011.h>
void uart_init(int idx)
{
@@ -27,12 +25,19 @@ void uart_init(int idx)
void uart_tx_byte(int idx, unsigned char data)
{
- unsigned int *uart_base = uart_platform_baseptr(idx);
- pl011_uart_tx_byte(uart_base, data);
+ struct pl011_uart *regs = uart_platform_baseptr(idx);
+
+ write8(&regs->dr, data);
+ uart_tx_flush(idx);
}
void uart_tx_flush(int idx)
{
+ struct pl011_uart *regs = uart_platform_baseptr(idx);
+
+ /* FIXME: add a timeout */
+ while (!(read32(&regs->fr) & PL011_UARTFR_TXFE))
+ ;
}
unsigned char uart_rx_byte(int idx)
diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h
new file mode 100644
index 0000000000..9247ef7725
--- /dev/null
+++ b/src/drivers/uart/pl011.h
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __DRIVERS_UART_PL011_H
+#define __DRIVERS_UART_PL011_H
+
+#include <inttypes.h>
+#include <types.h>
+
+/* PL011 r1p5 registers */
+struct pl011_uart {
+ u32 dr;
+ u32 rsr_ecr;
+ u8 rsvd1[0x10];
+ u32 fr;
+ u8 rsvd2[0x4];
+ u32 ilpr;
+ u32 ibrd;
+ u32 fbrd;
+ u32 lcr_h;
+ u32 cr;
+ u32 ifls;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+ u8 rsvd3[0xf94];
+ u32 periphid0;
+ u32 periphid1;
+ u32 periphid2;
+ u32 periphid3;
+ u32 cellid0;
+ u32 cellid1;
+ u32 cellid2;
+ u32 cellid3;
+};
+check_member(pl011_uart, cellid3, 0xffc);
+
+/*************************************************************************/
+/* Bit definitions from arm-trusted-firmware/include/drivers/arm/pl011.h */
+/*************************************************************************/
+/* Flag reg bits */
+#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */
+#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */
+#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */
+#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */
+#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */
+#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */
+#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */
+#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */
+#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */
+
+#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in
+ UARTFR register */
+#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in
+ UARTFR register */
+#define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR
+ register */
+
+/* Control reg bits */
+#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control
+ enable */
+#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control
+ enable */
+#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
+#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */
+#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */
+#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */
+#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */
+#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */
+
+/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
+#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
+
+/* Line Control Register Bits */
+#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */
+#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
+#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
+#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
+#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
+#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */
+#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */
+#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */
+#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
+#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
+
+#endif /* ! __DRIVERS_UART_PL011_H */