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-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
index e30da3af4d..6484330ae1 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
@@ -8,6 +8,22 @@ chip soc/intel/cannonlake
register "SaGv" = "SaGv_Enabled"
register "ScsEmmcHs400Enabled" = "1"
register "HeciEnabled" = "1"
+ register "s0ix_enable" = "1"
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+ }"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"