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-rw-r--r--src/soc/intel/common/block/cse/cse_lite.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index c29b56c407..a8948be202 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -663,7 +663,11 @@ void cse_fw_sync(void *unused)
}
#if CONFIG(SOC_INTEL_TIGERLAKE)
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);
+/*
+ * This needs to happen after the MRC cache write to avoid a 2nd
+ * memory training sequence.
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL);
#else
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
#endif