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-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.h8
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dfbdfb812d..4139570f64 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -212,6 +212,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
if (config->PcieRpAspm[i])
params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+ if (config->pcie_rp_l1substates[i])
+ params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
}
/*
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index fa30c1dfcf..5befb01a91 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -264,6 +264,14 @@ struct soc_intel_skylake_config {
AspmAutoConfig,
} PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
+ /* PCIe RP L1 substate */
+ enum {
+ L1SS_Default,
+ L1SS_Disabled,
+ L1SS_L1_1,
+ L1SS_L1_2,
+ } pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS];
+
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];