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-rw-r--r--src/soc/amd/common/block/cpu/Kconfig3
-rw-r--r--src/soc/amd/common/block/pi/Kconfig3
2 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 5941599df0..f6756e18f8 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -8,3 +8,6 @@ config SOC_AMD_COMMON_BLOCK_CAR
it may not be appropriate for a romstage implementation without
additional consideration. If this option is not used, the SOC must
implement these functions separately.
+ This is only used for AMD CPU before family 17h. From family 17h on
+ the RAM is already initialized by the PSP before the x86 cores are
+ released from reset.
diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig
index f0917bb767..cf8c79ae50 100644
--- a/src/soc/amd/common/block/pi/Kconfig
+++ b/src/soc/amd/common/block/pi/Kconfig
@@ -3,7 +3,8 @@ config SOC_AMD_COMMON_BLOCK_PI
select HAVE_DEBUG_RAM_SETUP
default n
help
- This option builds functions that interface AMD's AGESA.
+ This option builds functions that interface AMD's AGESA reference
+ code packaged in the binaryPI form.
if SOC_AMD_COMMON_BLOCK_PI