diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/config/Options.lb | 11 | ||||
| -rw-r--r-- | src/console/Config.lb | 4 | ||||
| -rw-r--r-- | src/console/usbdebug_direct_console.c | 58 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 12 | ||||
| -rw-r--r-- | src/include/ehci.h | 132 | ||||
| -rw-r--r-- | src/include/usb_ch9.h | 83 | ||||
| -rw-r--r-- | src/include/usbdebug_direct.h | 17 | ||||
| -rw-r--r-- | src/lib/Config.lb | 6 | ||||
| -rw-r--r-- | src/lib/usbdebug_direct.c | 539 | ||||
| -rw-r--r-- | src/pc80/usbdebug_direct_serial.c | 25 |
10 files changed, 887 insertions, 0 deletions
diff --git a/src/config/Options.lb b/src/config/Options.lb index 0b3c3acf71..d1645cdcf6 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -442,6 +442,11 @@ define CONFIG_CONSOLE_SERIAL8250 export always comment "Log messages to 8250 uart based serial console" end +define CONFIG_USBDEBUG_DIRECT + default 0 + export always + comment "Log messages to ehci debug port console" +end define DEFAULT_CONSOLE_LOGLEVEL default 7 export always @@ -999,6 +1004,12 @@ define CONFIG_PCI_64BIT_PREF_MEM comment "allow PCI device get 4G above Region as pref mem" end +define CONFIG_AGESA + default 0 + export always + comment "use AMD AGESA to init RAM instead of native code" +end + define CONFIG_VIDEO_MB default none export used diff --git a/src/console/Config.lb b/src/console/Config.lb index daba367f94..7a1672e494 100644 --- a/src/console/Config.lb +++ b/src/console/Config.lb @@ -1,4 +1,5 @@ uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_USBDEBUG_DIRECT uses CONFIG_CONSOLE_VGA uses CONFIG_CONSOLE_BTEXT uses CONFIG_CONSOLE_LOGBUF @@ -9,6 +10,9 @@ object printk.o if CONFIG_CONSOLE_SERIAL8250 driver uart8250_console.o end +if CONFIG_USBDEBUG_DIRECT + driver usbdebug_direct_console.o +end if CONFIG_CONSOLE_VGA driver vga_console.o end diff --git a/src/console/usbdebug_direct_console.c b/src/console/usbdebug_direct_console.c new file mode 100644 index 0000000000..172d5c8b55 --- /dev/null +++ b/src/console/usbdebug_direct_console.c @@ -0,0 +1,58 @@ +#include <console/console.h> +#include <usbdebug_direct.h> +#include <pc80/mc146818rtc.h> + +struct ehci_debug_info dbg_info; + +void set_ehci_base(unsigned ehci_base) +{ + unsigned diff; + if(!dbg_info.ehci_debug) return; + diff = dbg_info.ehci_caps - ehci_base; + dbg_info.ehci_regs -= diff; + dbg_info.ehci_debug -= diff; + dbg_info.ehci_caps = ehci_base; +} +void set_ehci_debug(unsigned ehci_debug) +{ + dbg_info.ehci_debug = ehci_debug; +} + +unsigned get_ehci_debug(void) +{ + return dbg_info.ehci_debug; +} + +static void dbgp_init(void) +{ + struct ehci_debug_info *dbg_infox; + dbg_infox = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM + memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info) ); +} + +static void dbgp_tx_byte(unsigned char data) +{ + if(dbg_info.ehci_debug) + dbgp_bulk_write_x(&dbg_info,&data,1); +} + +static unsigned char dbgp_rx_byte(void) +{ + unsigned char data = 0xff; + if(dbg_info.ehci_debug) + dbgp_bulk_read_x(&dbg_info,&data,1); + return data; +} + +static int dbgp_tst_byte(void) +{ + return dbg_info.ehci_debug; +} + +static struct console_driver usbdebug_direct_console __console = { + .init = dbgp_init, + .tx_byte = dbgp_tx_byte, + .rx_byte = dbgp_rx_byte, + .tst_byte = dbgp_tst_byte, +}; + diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index f97f68672f..e671975e42 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -546,6 +546,8 @@ static void amd_set_name_string_f(device_t dev) extern void model_fxx_update_microcode(unsigned cpu_deviceid); int init_processor_name(void); +static unsigned ehci_debug_addr; + void model_fxx_init(device_t dev) { unsigned long i; @@ -565,11 +567,21 @@ void model_fxx_init(device_t dev) } #endif +#if CONFIG_USBDEBUG_DIRECT + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + /* Update the microcode */ model_fxx_update_microcode(dev->device); diff --git a/src/include/ehci.h b/src/include/ehci.h new file mode 100644 index 0000000000..ed54b7e347 --- /dev/null +++ b/src/include/ehci.h @@ -0,0 +1,132 @@ +#ifndef EHCI_H +#define EHCI_H + +struct ehci_caps { + /* these fields are specified as 8 and 16 bit registers, + * but some hosts can't perform 8 or 16 bit PCI accesses. + */ + u32 hc_capbase; +#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ +#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ + u32 hcs_params; /* HCSPARAMS - offset 0x4 */ +#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ +#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ +#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ +#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ +#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ +#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ +#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ + + u32 hcc_params; /* HCCPARAMS - offset 0x8 */ +#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ +#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ +#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ +#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ +#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ +#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ + u8 portroute [8]; /* nibbles for routing - offset 0xC */ +} __attribute__ ((packed)); + +/* Section 2.3 Host Controller Operational Registers */ +struct ehci_regs { + + /* USBCMD: offset 0x00 */ + u32 command; +/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ +#define CMD_PARK (1<<11) /* enable "park" on async qh */ +#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ +#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ +#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ +#define CMD_ASE (1<<5) /* async schedule enable */ +#define CMD_PSE (1<<4) /* periodic schedule enable */ +/* 3:2 is periodic frame list size */ +#define CMD_RESET (1<<1) /* reset HC not bus */ +#define CMD_RUN (1<<0) /* start/stop HC */ + + /* USBSTS: offset 0x04 */ + u32 status; +#define STS_ASS (1<<15) /* Async Schedule Status */ +#define STS_PSS (1<<14) /* Periodic Schedule Status */ +#define STS_RECL (1<<13) /* Reclamation */ +#define STS_HALT (1<<12) /* Not running (any reason) */ +/* some bits reserved */ + /* these STS_* flags are also intr_enable bits (USBINTR) */ +#define STS_IAA (1<<5) /* Interrupted on async advance */ +#define STS_FATAL (1<<4) /* such as some PCI access errors */ +#define STS_FLR (1<<3) /* frame list rolled over */ +#define STS_PCD (1<<2) /* port change detect */ +#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ +#define STS_INT (1<<0) /* "normal" completion (short, ...) */ + + /* USBINTR: offset 0x08 */ + u32 intr_enable; + + /* FRINDEX: offset 0x0C */ + u32 frame_index; /* current microframe number */ + /* CTRLDSSEGMENT: offset 0x10 */ + u32 segment; /* address bits 63:32 if needed */ + /* PERIODICLISTBASE: offset 0x14 */ + u32 frame_list; /* points to periodic list */ + /* ASYNCLISTADDR: offset 0x18 */ + u32 async_next; /* address of next async queue head */ + + u32 reserved [9]; + + /* CONFIGFLAG: offset 0x40 */ + u32 configured_flag; +#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ + + /* PORTSC: offset 0x44 */ + u32 port_status [0]; /* up to N_PORTS */ +/* 31:23 reserved */ +#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ +#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ +#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ +/* 19:16 for port testing */ +#define PORT_LED_OFF (0<<14) +#define PORT_LED_AMBER (1<<14) +#define PORT_LED_GREEN (2<<14) +#define PORT_LED_MASK (3<<14) +#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ +#define PORT_POWER (1<<12) /* true: has power (see PPC) */ +#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ +/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ +/* 9 reserved */ +#define PORT_RESET (1<<8) /* reset port */ +#define PORT_SUSPEND (1<<7) /* suspend port */ +#define PORT_RESUME (1<<6) /* resume it */ +#define PORT_OCC (1<<5) /* over current change */ +#define PORT_OC (1<<4) /* over current active */ +#define PORT_PEC (1<<3) /* port enable change */ +#define PORT_PE (1<<2) /* port enable */ +#define PORT_CSC (1<<1) /* connect status change */ +#define PORT_CONNECT (1<<0) /* device connected */ +#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) +} __attribute__ ((packed)); + +/* Appendix C, Debug port ... intended for use with special "debug devices" + * that can help if there's no serial console. (nonstandard enumeration.) + */ +struct ehci_dbg_port { + u32 control; +#define DBGP_OWNER (1<<30) +#define DBGP_ENABLED (1<<28) +#define DBGP_DONE (1<<16) +#define DBGP_INUSE (1<<10) +#define DBGP_ERRCODE(x) (((x)>>7)&0x07) +# define DBGP_ERR_BAD 1 +# define DBGP_ERR_SIGNAL 2 +#define DBGP_ERROR (1<<6) +#define DBGP_GO (1<<5) +#define DBGP_OUT (1<<4) +#define DBGP_LEN(x) (((x)>>0)&0x0f) + u32 pids; +#define DBGP_PID_GET(x) (((x)>>16)&0xff) +#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) + u32 data03; + u32 data47; + u32 address; +#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) +} __attribute__ ((packed)); + +#endif diff --git a/src/include/usb_ch9.h b/src/include/usb_ch9.h new file mode 100644 index 0000000000..13aa391cb3 --- /dev/null +++ b/src/include/usb_ch9.h @@ -0,0 +1,83 @@ +#ifndef USB_CH9_H +#define USB_CH9_H + +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ + +/* + * USB types, the second of three bRequestType fields + */ +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) +/* + * USB recipients, the third of three bRequestType fields + */ +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 +/* From Wireless USB 1.0 */ +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05 + +/* + * Standard requests, for the bRequest field of a SETUP packet. + * + * These are qualified by the bRequestType field, so that for example + * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved + * by a GET_STATUS request. + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_RPIPE_ABORT 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_RPIPE_RESET 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17 + +#define USB_DT_DEBUG 0x0a + +#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ + +//frim usb_ch9.h +struct usb_ctrlrequest { + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} __attribute__ ((packed)); + +struct usb_debug_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + /* bulk endpoints with 8 byte maxpacket */ + uint8_t bDebugInEndpoint; + uint8_t bDebugOutEndpoint; +}; + +#endif + diff --git a/src/include/usbdebug_direct.h b/src/include/usbdebug_direct.h new file mode 100644 index 0000000000..1790b1508e --- /dev/null +++ b/src/include/usbdebug_direct.h @@ -0,0 +1,17 @@ +#ifndef USBDEBUG_DIRECT_H +#define USBDEBUG_DIRECT_H + +struct ehci_debug_info { + void *ehci_caps; + void *ehci_regs; + void *ehci_debug; + unsigned devnum; + unsigned endpoint_out; + unsigned endpoint_in; +}; +extern int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); +extern int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); +extern void set_ehci_base(unsigned ehci_base); +extern void set_ehci_debug(unsigned ehci_deug); +extern unsigned get_ehci_debug(void); +#endif diff --git a/src/lib/Config.lb b/src/lib/Config.lb index b2c2821800..7dfc16b82d 100644 --- a/src/lib/Config.lb +++ b/src/lib/Config.lb @@ -1,9 +1,15 @@ uses HAVE_FALLBACK_BOOT uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR +uses CONFIG_USBDEBUG_DIRECT object clog2.o object uart8250.o + +if CONFIG_USBDEBUG_DIRECT + object usbdebug_direct.o +end + object memset.o object memcpy.o object memcmp.o diff --git a/src/lib/usbdebug_direct.c b/src/lib/usbdebug_direct.c new file mode 100644 index 0000000000..4b9affea93 --- /dev/null +++ b/src/lib/usbdebug_direct.c @@ -0,0 +1,539 @@ +/* + * Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * 2006.12.10 yhlu moved it to LinuxBIOS and use struct instead + */ +#ifndef __ROMCC__ +#include <console/console.h> +#else +#if CONFIG_USE_PRINTK_IN_CAR==0 +#define printk_debug(fmt, arg...) do {} while(0) +#endif +#endif + + +#include <arch/io.h> + +#include <usb_ch9.h> +#include <ehci.h> +#include <usbdebug_direct.h> + +#define USB_DEBUG_DEVNUM 127 + +#define DBGP_DATA_TOGGLE 0x8800 +#define DBGP_PID_UPDATE(x, tok) \ + ((((x) ^ DBGP_DATA_TOGGLE) & 0xffff00) | ((tok) & 0xff)) + +#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f)) +/* + * USB Packet IDs (PIDs) + */ + +/* token */ +#define USB_PID_OUT 0xe1 +#define USB_PID_IN 0x69 +#define USB_PID_SOF 0xa5 +#define USB_PID_SETUP 0x2d +/* handshake */ +#define USB_PID_ACK 0xd2 +#define USB_PID_NAK 0x5a +#define USB_PID_STALL 0x1e +#define USB_PID_NYET 0x96 +/* data */ +#define USB_PID_DATA0 0xc3 +#define USB_PID_DATA1 0x4b +#define USB_PID_DATA2 0x87 +#define USB_PID_MDATA 0x0f +/* Special */ +#define USB_PID_PREAMBLE 0x3c +#define USB_PID_ERR 0x3c +#define USB_PID_SPLIT 0x78 +#define USB_PID_PING 0xb4 +#define USB_PID_UNDEF_0 0xf0 + +#define USB_PID_DATA_TOGGLE 0x88 +#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE) + +#define PCI_CAP_ID_EHCI_DEBUG 0xa + +#define HUB_ROOT_RESET_TIME 50 /* times are in msec */ +#define HUB_SHORT_RESET_TIME 10 +#define HUB_LONG_RESET_TIME 200 +#define HUB_RESET_TIMEOUT 500 + +#define DBGP_MAX_PACKET 8 + +static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) +{ + unsigned ctrl; + int loop = 0x100000; + do { + ctrl = readl(&ehci_debug->control); + /* Stop when the transaction is finished */ + if (ctrl & DBGP_DONE) + break; + } while(--loop>0); + + if (!loop) return -1000; + + /* Now that we have observed the completed transaction, + * clear the done bit. + */ + writel(ctrl | DBGP_DONE, &ehci_debug->control); + return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl); +} + +static void dbgp_mdelay(int ms) +{ + int i; + while (ms--) { + for (i = 0; i < 1000; i++) + outb(0x1, 0x80); + } +} + +static void dbgp_breath(void) +{ + /* Sleep to give the debug port a chance to breathe */ +} + +static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, unsigned ctrl) +{ + unsigned pids, lpid; + int ret; + + int loop = 3; +retry: + writel(ctrl | DBGP_GO, &ehci_debug->control); + ret = dbgp_wait_until_complete(ehci_debug); + pids = readl(&ehci_debug->pids); + lpid = DBGP_PID_GET(pids); + + if (ret < 0) + return ret; + + /* If the port is getting full or it has dropped data + * start pacing ourselves, not necessary but it's friendly. + */ + if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET)) + dbgp_breath(); + + /* If I get a NACK reissue the transmission */ + if (lpid == USB_PID_NAK) { + if (--loop > 0) goto retry; + } + + return ret; +} + +static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size) +{ + const unsigned char *bytes = buf; + unsigned lo, hi; + int i; + lo = hi = 0; + for (i = 0; i < 4 && i < size; i++) + lo |= bytes[i] << (8*i); + for (; i < 8 && i < size; i++) + hi |= bytes[i] << (8*(i - 4)); + writel(lo, &ehci_debug->data03); + writel(hi, &ehci_debug->data47); +} + +static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size) +{ + unsigned char *bytes = buf; + unsigned lo, hi; + int i; + lo = readl(&ehci_debug->data03); + hi = readl(&ehci_debug->data47); + for (i = 0; i < 4 && i < size; i++) + bytes[i] = (lo >> (8*i)) & 0xff; + for (; i < 8 && i < size; i++) + bytes[i] = (hi >> (8*(i - 4))) & 0xff; +} + +static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, unsigned endpoint, const char *bytes, int size) +{ + unsigned pids, addr, ctrl; + int ret; + if (size > DBGP_MAX_PACKET) + return -1; + + addr = DBGP_EPADDR(devnum, endpoint); + + pids = readl(&ehci_debug->pids); + pids = DBGP_PID_UPDATE(pids, USB_PID_OUT); + + ctrl = readl(&ehci_debug->control); + ctrl = DBGP_LEN_UPDATE(ctrl, size); + ctrl |= DBGP_OUT; + ctrl |= DBGP_GO; + + dbgp_set_data(ehci_debug, bytes, size); + writel(addr, &ehci_debug->address); + writel(pids, &ehci_debug->pids); + + ret = dbgp_wait_until_done(ehci_debug, ctrl); + if (ret < 0) { + return ret; + } + return ret; +} + +int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size) +{ + return dbgp_bulk_write(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_out, bytes, size); +} + +static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, unsigned endpoint, void *data, int size) +{ + unsigned pids, addr, ctrl; + int ret; + + if (size > DBGP_MAX_PACKET) + return -1; + + addr = DBGP_EPADDR(devnum, endpoint); + + pids = readl(&ehci_debug->pids); + pids = DBGP_PID_UPDATE(pids, USB_PID_IN); + + ctrl = readl(&ehci_debug->control); + ctrl = DBGP_LEN_UPDATE(ctrl, size); + ctrl &= ~DBGP_OUT; + ctrl |= DBGP_GO; + + writel(addr, &ehci_debug->address); + writel(pids, &ehci_debug->pids); + ret = dbgp_wait_until_done(ehci_debug, ctrl); + if (ret < 0) + return ret; + if (size > ret) + size = ret; + dbgp_get_data(ehci_debug, data, size); + return ret; +} +int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size) +{ + return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_in, data, size); +} + +static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request, + int value, int index, void *data, int size) +{ + unsigned pids, addr, ctrl; + struct usb_ctrlrequest req; + int read; + int ret; + + read = (requesttype & USB_DIR_IN) != 0; + if (size > (read?DBGP_MAX_PACKET:0)) + return -1; + + /* Compute the control message */ + req.bRequestType = requesttype; + req.bRequest = request; + req.wValue = value; + req.wIndex = index; + req.wLength = size; + + pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP); + addr = DBGP_EPADDR(devnum, 0); + + ctrl = readl(&ehci_debug->control); + ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req)); + ctrl |= DBGP_OUT; + ctrl |= DBGP_GO; + + /* Send the setup message */ + dbgp_set_data(ehci_debug, &req, sizeof(req)); + writel(addr, &ehci_debug->address); + writel(pids, &ehci_debug->pids); + ret = dbgp_wait_until_done(ehci_debug, ctrl); + if (ret < 0) + return ret; + + + /* Read the result */ + ret = dbgp_bulk_read(ehci_debug, devnum, 0, data, size); + return ret; +} + +static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) +{ + unsigned portsc; + unsigned delay_time, delay; + int loop; + + /* Reset the usb debug port */ + portsc = readl(&ehci_regs->port_status[port - 1]); + portsc &= ~PORT_PE; + portsc |= PORT_RESET; + writel(portsc, &ehci_regs->port_status[port - 1]); + + delay = HUB_ROOT_RESET_TIME; + for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT; + delay_time += delay) { + dbgp_mdelay(delay); + + portsc = readl(&ehci_regs->port_status[port - 1]); + if (portsc & PORT_RESET) { + /* force reset to complete */ + loop = 2; + writel(portsc & ~(PORT_RWC_BITS | PORT_RESET), + &ehci_regs->port_status[port - 1]); + do { + dbgp_mdelay(delay); + portsc = readl(&ehci_regs->port_status[port - 1]); + delay_time += delay; + } while ((portsc & PORT_RESET) && (--loop > 0)); + if (!loop) { + printk_debug("ehci_reset_port forced done"); + } + } + + /* Device went away? */ + if (!(portsc & PORT_CONNECT)) + return -107;//-ENOTCONN; + + /* bomb out completely if something weird happend */ + if ((portsc & PORT_CSC)) + return -22;//-EINVAL; + + /* If we've finished resetting, then break out of the loop */ + if (!(portsc & PORT_RESET) && (portsc & PORT_PE)) + return 0; + } + return -16;//-EBUSY; +} + +static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) +{ + unsigned status; + int ret, reps; + for (reps = 0; reps < 3; reps++) { + dbgp_mdelay(100); + status = readl(&ehci_regs->status); + if (status & STS_PCD) { + ret = ehci_reset_port(ehci_regs, port); + if (ret == 0) + return 0; + } + } + return -107; //-ENOTCONN; +} + + +#define DBGP_DEBUG 1 +#if DBGP_DEBUG +# define dbgp_printk printk_debug +#else +#define dbgp_printk(fmt, arg...) do {} while(0) +#endif +static void usbdebug_direct_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) +{ + struct ehci_caps *ehci_caps; + struct ehci_regs *ehci_regs; + struct ehci_dbg_port *ehci_debug; + unsigned dbgp_endpoint_out; + unsigned dbgp_endpoint_in; + struct usb_debug_descriptor dbgp_desc; + unsigned ctrl, devnum; + int ret; + unsigned delay_time, delay; + int loop; + + unsigned cmd, status, portsc, hcs_params, debug_port, n_ports, new_debug_port; + int i; + unsigned port_map_tried; + + unsigned playtimes = 3; + + ehci_caps = (struct ehci_caps *)ehci_bar; + ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase))); + ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); + + info->ehci_debug = (void *)0; + +try_next_time: + port_map_tried = 0; + +try_next_port: + hcs_params = readl(&ehci_caps->hcs_params); + debug_port = HCS_DEBUG_PORT(hcs_params); + n_ports = HCS_N_PORTS(hcs_params); + + dbgp_printk("debug_port: %d\n", debug_port); + dbgp_printk("n_ports: %d\n", n_ports); + +#if 0 + for (i = 1; i <= n_ports; i++) { + portsc = readl(&ehci_regs->port_status[i-1]); + dbgp_printk("portstatus%d: %08x\n", i, portsc); + } +#endif + + if(port_map_tried && (new_debug_port!=debug_port)) { + if(--playtimes) { + set_debug_port(debug_port); + goto try_next_time; + } + return; + } + + /* Reset the EHCI controller */ + loop = 10; + cmd = readl(&ehci_regs->command); + cmd |= CMD_RESET; + writel(cmd, &ehci_regs->command); + do { + cmd = readl(&ehci_regs->command); + } while ((cmd & CMD_RESET) && (--loop > 0)); + + if(!loop) { + dbgp_printk("can not reset ehci\n"); + return; + } + dbgp_printk("ehci reset done\n"); + + /* Claim ownership, but do not enable yet */ + ctrl = readl(&ehci_debug->control); + ctrl |= DBGP_OWNER; + ctrl &= ~(DBGP_ENABLED | DBGP_INUSE); + writel(ctrl, &ehci_debug->control); + + /* Start the ehci running */ + cmd = readl(&ehci_regs->command); + cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET); + cmd |= CMD_RUN; + writel(cmd, &ehci_regs->command); + + /* Ensure everything is routed to the EHCI */ + writel(FLAG_CF, &ehci_regs->configured_flag); + + /* Wait until the controller is no longer halted */ + loop = 10; + do { + status = readl(&ehci_regs->status); + } while ((status & STS_HALT) && (--loop>0)); + + if(!loop) { + dbgp_printk("ehci can be started\n"); + return; + } + dbgp_printk("ehci started\n"); + + /* Wait for a device to show up in the debug port */ + ret = ehci_wait_for_port(ehci_regs, debug_port); + if (ret < 0) { + dbgp_printk("No device found in debug port %d\n", debug_port); + goto next_debug_port; + } + dbgp_printk("ehci wait for port done\n"); + + /* Enable the debug port */ + ctrl = readl(&ehci_debug->control); + ctrl |= DBGP_CLAIM; + writel(ctrl, &ehci_debug->control); + ctrl = readl(&ehci_debug->control); + if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) { + dbgp_printk("No device in debug port\n"); + writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control); + goto err; + } + dbgp_printk("debug ported enabled\n"); + + /* Completely transfer the debug device to the debug controller */ + portsc = readl(&ehci_regs->port_status[debug_port - 1]); + portsc &= ~PORT_PE; + writel(portsc, &ehci_regs->port_status[debug_port - 1]); + + dbgp_mdelay(100); + + /* Find the debug device and make it device number 127 */ + for (devnum = 0; devnum <= 127; devnum++) { + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0, + &dbgp_desc, sizeof(dbgp_desc)); + if (ret > 0) + break; + } + if (devnum > 127) { + dbgp_printk("Could not find attached debug device\n"); + goto err; + } + if (ret < 0) { + dbgp_printk("Attached device is not a debug device\n"); + goto err; + } + dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint; + dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint; + + /* Move the device to 127 if it isn't already there */ + if (devnum != USB_DEBUG_DEVNUM) { + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, (void *)0, 0); + if (ret < 0) { + dbgp_printk("Could not move attached device to %d\n", + USB_DEBUG_DEVNUM); + goto err; + } + devnum = USB_DEBUG_DEVNUM; + dbgp_printk("debug device renamed to 127\n"); + } + + /* Enable the debug interface */ + ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, (void *)0, 0); + if (ret < 0) { + dbgp_printk(" Could not enable the debug device\n"); + goto err; + } + dbgp_printk("debug interface enabled\n"); + + /* Perform a small write to get the even/odd data state in sync + */ + ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ",1); + if (ret < 0) { + dbgp_printk("dbgp_bulk_write failed: %d\n", ret); + goto err; + } + dbgp_printk("small write doned\n"); + + info->ehci_caps = ehci_caps; + info->ehci_regs = ehci_regs; + info->ehci_debug = ehci_debug; + info->devnum = devnum; + info->endpoint_out = dbgp_endpoint_out; + info->endpoint_in = dbgp_endpoint_in; + + return; +err: + /* Things didn't work so remove my claim */ + ctrl = readl(&ehci_debug->control); + ctrl &= ~(DBGP_CLAIM | DBGP_OUT); + writel(ctrl, &ehci_debug->control); + +next_debug_port: + port_map_tried |= (1<<(debug_port-1)); + if(port_map_tried != ((1<<n_ports) -1)) { + new_debug_port = ((debug_port-1+1)%n_ports) + 1; + set_debug_port(new_debug_port); + goto try_next_port; + } + if(--playtimes) { + set_debug_port(debug_port); + goto try_next_time; + } + +} + + diff --git a/src/pc80/usbdebug_direct_serial.c b/src/pc80/usbdebug_direct_serial.c new file mode 100644 index 0000000000..e795349a22 --- /dev/null +++ b/src/pc80/usbdebug_direct_serial.c @@ -0,0 +1,25 @@ +#include <part/fallback_boot.h> +#include "../lib/usbdebug_direct.c" +static void early_usbdebug_direct_init(void) +{ + struct ehci_debug_info *dbg_info = + (struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); + + usbdebug_direct_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); +} +void usbdebug_direct_tx_byte(unsigned char data) +{ + struct ehci_debug_info *dbg_info; + dbg_info = (struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); // in Cache + if (dbg_info->ehci_debug) { + dbgp_bulk_write_x(dbg_info, &data, 1); + } +} +void usbdebug_direct_ram_tx_byte(unsigned char data) +{ + struct ehci_debug_info *dbg_info; + dbg_info = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM + if (dbg_info->ehci_debug) { + dbgp_bulk_write_x(dbg_info, &data, 1); + } +} |