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-rw-r--r--src/mainboard/broadcom/blast/romstage.c2
-rw-r--r--src/mainboard/hp/dl145_g3/romstage.c2
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/romstage.c2
-rw-r--r--src/mainboard/msi/ms9185/romstage.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/Kconfig1
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c21
-rw-r--r--src/southbridge/broadcom/bcm5785/bootblock.c5
7 files changed, 17 insertions, 18 deletions
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index b6cbc2f21c..e3791a79bf 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -10,7 +10,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@@ -82,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
- bcm5785_enable_rom();
bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index ff16b3f8bb..eeac3e5b6a 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -41,7 +41,6 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@@ -145,7 +144,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
- bcm5785_enable_rom();
bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index f167b925ac..ae9be8aeea 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -40,7 +40,6 @@
#include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
@@ -109,7 +108,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
- bcm5785_enable_rom();
bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index ffe728d3e5..a27fec0118 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -35,7 +35,6 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@@ -115,7 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
- bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig
index d72afd8d2c..dae9a63f2c 100644
--- a/src/southbridge/broadcom/bcm5785/Kconfig
+++ b/src/southbridge/broadcom/bcm5785/Kconfig
@@ -1,6 +1,7 @@
config SOUTHBRIDGE_BROADCOM_BCM5785
bool
select HAVE_HARD_RESET
+ select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c b/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
index c5385ae257..1cd28498b9 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
@@ -18,17 +18,22 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
static void bcm5785_enable_rom(void)
{
- unsigned char byte;
- device_t addr;
+ u8 byte;
+ device_t dev;
- /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
- /* Locate the BCM 5785 SB PCI Main */
- addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
+ PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
- /* Set the 4MB enable bit bit */
- byte = pci_read_config8(addr, 0x41);
+ /* Set the 4MB enable bits. */
+ byte = pci_read_config8(dev, 0x41);
byte |= 0x0e;
- pci_write_config8(addr, 0x41, byte);
+ pci_write_config8(dev, 0x41, byte);
}
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index 77bf231f5d..40201c6072 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -20,6 +20,7 @@
#include "bcm5785_enable_rom.c"
-static void bootblock_southbridge_init(void) {
- bcm5785_enable_rom();
+static void bootblock_southbridge_init(void)
+{
+ bcm5785_enable_rom();
}