diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 6 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 6 |
4 files changed, 17 insertions, 8 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 4e0f391d33..65da51631b 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -30,9 +30,6 @@ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) -/* Base address to cache all of Flash ROM, just below 4GB. */ -#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) - #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -380,6 +377,7 @@ no_msr_11e: movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax wrmsr +#if CONFIG_CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax @@ -389,6 +387,7 @@ no_msr_11e: rdmsr movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr +#endif post_code(0x39) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 33246ff5bb..9a2db37ef4 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -259,17 +259,19 @@ before_romstage: movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr +#if CONFIG_CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index bdefb21b59..82a568ac1e 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -191,15 +191,17 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ +#if CONFIG_CACHE_ROM_SIZE + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8b5cc281bc..58bee0412d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,6 +56,12 @@ void x86_setup_fixed_mtrrs(void); # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif + +#define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12) + #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif |