diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/quark/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index 61773d5d4c..1224bcc156 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -25,7 +25,8 @@ #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE /* I2C/GPIO Controller */ -#define I2C_GPIO_BASE_ADDRESS 0xa0020000 +#define I2C_BASE_ADDRESS 0xa0020000 +#define GPIO_BASE_ADDRESS 0xa0021000 /* * I/O port address space diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c4f9844754..c86c2eae3d 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -52,7 +52,8 @@ static const struct reg_script legacy_gpio_init[] = { static const struct reg_script i2c_gpio_controller_init[] = { /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, I2C_GPIO_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), REG_SCRIPT_END }; |